PICASTAR First LO Squarer
If you decide to use any of the information here, you will make
your PICASTAR non-standard. Even if you wish to do the changes on a
'new-build' STAR, please build it first using all the standard build
information, with no changes from the published design. Also you need
to calibrate it using all the excellent BASIC programmes, to verify
that it works correctly, before you modify it. This is what I did
If you do not 'RTFM' (read and use all
the PICASTAR documentation in the Yahoo! Groups Pic-a-Project
group) before you modify
your build in any way, then no-one will be able to help you to get your
own build working. You must
join this group in order to obtain (and be permitted to use) the design
information that you need. If you then need help (with an un-modified
STAR) you will get it by posting your problem on the picastar-users
If your STAR is modified in any way, then the very helpful people on
the picastar-users group will probably not be able to help you.
If things work so badly that you are unable to make it operate, then
consider asking first on the picastar-users
group. But read my suggestions anyway...
When I set about commissioning my newly built ComboStar (PICASTAR using
Glenn's excellent 'all-in-one' PCB) I found that the first mixer didn't
work properly, especially at the higher LO frequencies. I began by
looking at the logic drives to the H-bridge bus switches.
What I found was that, at low
LO frequencies, the squarer (IC503) buffer outputs on pins 8 and 11
were far from square waves; poor duty cycle with 'feathers' on
the transitions due to oscillations somewhere. At high LO frequencies,
nothing but a low-frequency relaxation waveform at both outputs. This
was clearly not any use, so the process of investigation began. Had I
used an incorrect component, or left something unsoldered?
To avoid any suggestion that I had 'built it wrongly' I replaced every
component of the squarer and the LO and its output filter, and measured
the new parts before fitting
them. I also used a
Fairchild rather than T.I. version of the 74AC86. It was exactly as
The purpose of the squarer is to produce a square wave at LO frequency
for operating an 'H-mode mixer' which is just 4 FETS in a H-bridge
chopping the incoming RF at LO frequency to produce the IF.
This whole thing (squarer plus H-mode switches) is a replacement for
the original diode double-balanced mixer, since switch-based mixers
have (it seems) better intercept & lower distortion. The original
modular diode mixer had 50R +7dBm LO port spec, which therefore became
for the squarer, but in reality the squarer needs volts, not
power, since it is a FET stage.
I present two levels of
improvement here. The first is
possible for anyone to do on
an existing PCB. The second requires
changes to board layout for good results and, although spectacular,
cannot be done retrospectively.
As a PICASTAR novice, I had not expected that there would be problems
in this area; it seemed as if no-one else had this problem. As time has
passed, I know that many constructors have had the same or similar
problems and have devised workarounds in many different ways, including
wholesale substitution of different circuitry. But I felt that it was
necessary to understand why this standard design didn't work for me,
and to try to fix it as non-invasively as possible. As a long-stop I
had in mind the possibility of using two of the amazing Analog Devices
'super-comparators', which can have internal hysteresis and can
directly drive the bus switches, but this was not my preferred route
since it would need board changes.
The original circuit, from Glenn's ComboBoard, is shown below for
When I refer to the SQUARER it is the two sections of IC503 with
low-numbered pins (left-hand side of the symbol in the schematic),
which is effectively an amplifier overdriven with
LO sine wave "Local Osc Input". The second part of IC503 (right-hand
side of the the schematic symbol) BUFFERs the
squarer output and produces anti-phase logic drives for the H-switches
of the mixer.
Brief Description of Squarer Circuit
In the schematic above, the 470R R508 acts as a 'grid stopper' to
isolate the LO Input coax
from the IC503 XOR input pin (I believe the original design uses 270R).
This reduces the likelihood of the track
coax acting as a resonator which can exacerbate oscillation by
providing phase shift at IC503 input (pin 2). Any such resonance is
heavily damped by the resistor. The 10k (R536) feeds back a voltage
averaged output of the squarer, presumably to provide some d.c. -ve
stabilise the input switching point.
The "BALANCE" potentiometer can move this bias point somewhat (but only
in one direction) and has been found useful by some constructors in
order to minimise 'birdies'.
R503 (56R) nominally terminates the LO Buffer and the short coax from
the DDS Filter, and
C507 (1nF) provides the necessary d.c. blocking for the XOR with its
roughly mid-rail threshold voltage.
Within IC503, two XOR sections (pins 1,2,3 and 4,5,6) are configured as
inverting and non-inverting respectively by strapping pins 1 and 5 to
opposite supplies. This gives the overall inverting configuration that
puts the feedback of the d.c. operating point in the correct inversion
See more about Gate
Thresholds in the Appendix
The averaging circuit R527, C533 at the squarer output (IC503 pin 6)
is, I believe, intended to set the bias for the input gate (IC503 pin
2) by averaging the rectangular wave at the output and feeding back the
mean level to the input pin via R526. The component values are chosen
remove the HF signal present at pin 5 of the XOR, just leaving a d.c.
level that is
nominally mid-rail for a square-wave, becoming less positive if the
too much of the cycle at 0v and vice versa. If the gate threshold were
at mid-rail, then this could be a good way to maintain an equal
mark:space at the output. We may expect the bias voltage to shift to
reflect the lack of squareness, thereby altering the response to
the incoming sine wave in such a way that the slope of the sine wave
moves relative to the CMOS threshold, nominally correcting the output
At least, this is the way it seems at first glance.
Of course, the CMOS gate threshold is only typically at mid-rail. It can be
between one third and two thirds of the rail and is still within
specification, according to the data-sheet.
So let us think about how the fed back bias is produced. It is an
averaged version of the squarer output (on pin 6 of the XOR). This
averaging is performed by the RC network consisting of R527 (10k) and
C533 (100nF), which has a time constant of 1000us, much longer than the
period of the lowest LO frequency (just over 10MHz, say 100ns).
This network feeds back the average value of the output waveform. But
we need a square-wave at the output, and the only ways that the average
can change are:
If the waveform is a
square-wave, the averager feeds back exactly half
the chip output excursion to bias the gate. For a nominal device, this
sounds fine at face value, but what if the chip threshold is not at
- The waveform deviates from square (1:1 mark:space),
- The chip output levels change.
If this were a self-biased linear op-amp circuit (let us say a voltage
follower), the negative feedback would act to hold the output at the
same voltage as the input and would be a representation of
the input. We have negative feedback - so what is different?
The difference is that the squarer is definitely not
circuit. It is
strongly overdriven and the output is a clipped and amplified version
of the input (the LO). The only way that the fed-back threshold voltage
can vary dynamically is for the waveform to change from being a
the mark:space ratio changes. In other words, in order to produce the
threshold voltage of the gate, which it must do if we are to produce a
square-wave, the output will not be a square-wave unless the threshold
just happens to be at one specific level.
There is a provision for a further modification of the fed-back voltage
in the presence of the Pot RV501 (500k) which forms a potential divider
at the averaging capacitor node. However, as designed, this adjuster
can only serve
to reduce the node voltage; it cannot increase it.
Because our desired output is a square-wave, we must adjust the pot
RV501 until the voltage fed back is equal to the gate input threshold,
so that the incoming a.c. coupled sine-wave is symmetrically clipped by
the circuit. Any bias voltage other than this will not produce a
square-wave at the output.
Since we can only use RV501 to reduce
the level produced by averaging
the output, there is no way that a square-wave will be produced if the
threshold of the chip is above the nominal mid-rail. It must then
produce a non-1:1 mark:space, which is not at all what we want.
Steve G7WAS found that he could
not obtain a square-wave at the output,
and modified his circuit as I describe below, to use RV501 across the
whole supply in order to allow any bias level to be set. With this he
was then easily able to set the potentiometer to produce a square-wave.
the pot setting was now at the device threshold, he was able to measure
the pot voltage and tell me the threshold of his own chip.
Steve said: "I modified the MR squarer by using the supply
rail and balance pot. It
cured the asymmetry see attached image; it is quite typical of all the
bands, some small variation with frequency. But much better than
original circuit which showed asymmetry when fully adjusted".
This is what Steve now obtains as
bus-switch drives (Note that one trace is inverted for clarity).
We might expect, then, that Steve's chip had a threshold above the
typical mid-rail level, which is impossible to compensate with the
original pot configuration.
He made some measurements:
Chip supply: 5.015V
Pot setting: 2.425V
So Steve's chip threshold was a fair bit lower than the mid-rail.
the original pot configuration provide adjustment, as we have expected?
The output waveform is averaged to provide the bias feedback, as
described. But remember - it is the output
waveform, not a swing between rails, that is averaged.
The apparent discrepancy is actually produced by the 'official mod' resistor RSQ1 (470R)
which loads the 'high' condition of the CMOS output and, together with
the 'on'-resistance of the PMOS FET that is trying to pull a high
level, reduces the high level at the pin to somewhat less than the
supply voltage. The low level is a good 0V, both from the chip and the
Taking the manufacturer's published data-sheet figures (for high output
level at 24mA for supplies
of 4.5V and 5.5V), there is a voltage drop in the PFET of 0.74V for
sink, at both supply values (4.5V and 5.5V).
Adjusting this linearly (the PFET is resistive in saturation) for a
load current of 10mA (approximate value
for a 470R load RSQ1 and 5V supply) we expect a drop of up to 0.31V in the upper (PMOS)
output FET in the gate.
This means, for Steve's case, with a supply of 5.015V, the output at
pin 6 would swing between 0V and
0.31)V, giving a mean value for a square-wave output of 2.35V
This 2.35V feedback is already below the gate threshold of Steve's chip
amount of adjusting the pot could ever cause the threshold to be
reached; it can only reduce the voltage in the standard
configuration. Therefore, because the input is biassed below threshold,
input LO waveform (a.c. coupled sine wave) spends more time above than
below the threshold. Because the squarer is inverting overall, this
means the output is 'low' for longer than it is 'high', which although
it allows a stable bias to be fed back, this is not as a result of
having a square-wave output.
So for Steve the pot connection 'as
a potentiometer' between the
supplies is the only way to obtain the square-wave he expects at pin 6.
This will apply to most constructors with chips that have even below
the typical 'mid-rail'
RSQ1 may have reduced the tendency for the stage to oscillate, but it
also reduces the chances of getting a square-wave out.
The solution is to re-deploy the Potentiometer as described below,
with the pot across the supply-ground, to provide an adjustable voltage
that tracks the chip threshold (both are a proportion of the supply)
and permits the full range of possible chip threshold to be compensated.
New connection for RV501
A much better bias arrangement would be to put RV501 as a potential
divider across the supply rail, and use it as the means of setting the
chip bias voltage (as a part of the supply). Forget using the output
signal in feedback - leave it open loop. With an AC86, the
threshold tracks the supply voltage anyway (it a percentage of the
supply), which is what the potentiometer also does.
The only 'better' way would be to derive a die-dependent threshold
voltage from an
otherwise unused gate on the same die, which is often done when
single-stage inverters are used. Sadly, the chances of linearly
self-biasing a multi-stage gate (like the XOR, or a 'buffered'
are zero, it simply won't happen; the stage simply oscillates at high
frequency, which is not
what we want. In any case, the XOR is a highly complex gate with both
inverting and non-inverting paths; it is simply unsuitable for
threshold generation (or any other linear biassing). In the sketch
below I have not drawn R529 (22k)
which is in series with the pot wiper; this can remain in circuit
between the wiper and the C533/R526 junction:
This ('open-loop' bias using RV501) is probably the best we can do.
It may be 'open-loop', but still tracks the supply in the same was as
does the chip threshold - both are a proportion of the supply voltage,
and when the pot is set to produce the chip threshold they are both at
the identical proportion).
Physically the change is not ridiculously difficult. One end
of RV510 track is at ground, and by removing R529 we can link the other
end of the pot track to the 5v supply. But at present the wiper is
connected to ground. We must remove this connection, to be able to use
it as the variable bias voltage feed. Remove the original feedback
resistor from the pin-6 output (R527, 10k) completely, since we
don't want the output squareness
to set the bias point. Then connect the liberated pot wiper to C533, to
inject the bias. Perhaps the easiest practical way is to remove the pot
RV510 and glue it to the board surface to give access to the lead-out
wires, then connect them appropriately.
All we need do then is to adjust RV501 for a
symmetrical square wave from IC503 pin 6. How? Maybe using a
timer-counter to measure both high & low intervals. Maybe by using
a 'scope to get close and then tuning RV501 for
'best results'. How did you intend verifying that it was 50:50 before
you read this? Do it like that. Steve G7WAS used a scope that displays duty-cycle.
Beware, though, of trying to use an RC averager to set duty-cycle for
half-rail - the load of RSQ1 causes an incorrect result unless it is
done at either pin 8 or pin 11, where the logic level is buffered.
Note that this method is functionally little different to the present
design. There is absolutely no 'auto corrective feedback' such as might
just possibly have existed with the original (if we permit the output
cycle to vary, which we don't), otherwise instead of using the output
half-rail averaged signal as the pot feed, we use the full
supply. This allows us to adjust the circuit for almost any device
threshold voltage (but at extremes,
beware that the tips of the
LO sine wave must not exceed the supply/ground voltages or
and poor performance must result as the protection diodes conduct.
74ACT86, which can have an
input threshold voltage as low as 0.8V).
Once you have done this change, there is no longer any negative
feedback from the squarer output (pin 6) to the input (pin 2) through
R527 and R526. This removes the unstable feedback path that previously
provided a low-frequency rectangular wave oscillation at the output if
the LO is absent. You should expect that the residual difference
between the bias from the pot and the chip threshold will be amplified
by the cascaded XOR stages and will drive the output to a supply rail
(if it drives high at the output, remember that RSQ1 will cause the
level to fall short of Vcc by up to 0.3V, as described earlier). There
is no feedback, so no unstable feedback loop and no L.F. instability as there was before.
Steve G7WAS confirms that his own Picastar, now with the pot
behaves exactly like this. He has adjusted for the best square-wave and
now, in the absence of LO input, the pin 6 output sits at 4.917V for a
supply of 5.019V, which is a shortfall of 0.1V as a result of driving
RSQ1 (the chip spec worst case would give a drop of 0.3V). In this
condition of "no-LO", RSQ1 (470R) is dissipating 53mW, which is safely
within the 100mW rating of most 0603-body resistors, although some
low-cost parts. e.g. from Multicomp, are rated at 63mW which is a bit
close (you will be OK with 0805 or 1206 style).
Steve has kindly
measured the XOR body temperature using a thermocouple meter, with the
LO signal - 'Pot Mod' done.
|Temperature after 15mins
This lower temperature with no LO signal indicates that there is no
serious effect from internal instability when the RV510 pot mod is done
The Squarer receives input sine-waves from the LO. Its task is to
the sine-wave into a logic level capable of operating the next stages.
In order to do this, it must produce clean logic signals from the
incoming sine-wave at all frequencies of interest. For a standard
Picastar the LO is always higher than the signal frequency and the IF
the first mixer is usually close to 10.7MHz, so the LO can be
considered to produce signals from about 12MHz to 40MHz. We are told
that an LO level of +7dBm is required. Certainly, my original LO level
of 2 to 3 dBm did not result in proper operation of the squarer, but once I had solved that and obtained +7dBm it did
seem to work - but with what margin?
There was still
a tendency for the squarer to produce slight feathery oscillations at
the output transitions; maybe there were even more significant internal
could not be seen at the output. These may account for the
'birdies' that are alterable by adjusting RV501 - also the 'later
addition' of RSQ1 as a heavy load on the squarer (pin 6) acts both to
reduce the gain of the second gate and shift its input threshold
slightly, both of which will help prevent parasitics at transitions.
The residual parasitics were reduced by some
simple changes, as follows:
The circuit behaves as before, but now the new 100R directly at pin 2
of IC 503 provides isolation of the entire long track. The fed back
from R526 now feeds through this new resistor, but the function is
identical. 100R effectively in series with 10k (R526) is insignificant.
Otherwise, the circuit is exactly as before (but the value of input
resistor is reduced).
- The 470R series resistor R508 was replaced with a 0R (note that
the original design value was 270R; I don't know why this is changed to
470R for the Combo),
- IC503 pin 2 was lifted from the pad (I had done this anyway for
transformer addition) and a 100R 0603 inserted between the lifted pin
and the pad. This replaces the effect of R508.
A value of 100R at IC503 pin 2 still gives good isolation of the long
connection from the LO, but has the following advantage over the
original 470R (R508):
capacitance of IC503 is specified as <6pF (from the Philips
data sheet). This
capacitance, plus tracking strays, together with R508 acts as a
low-pass element. With the
original 470R, this is -3dB at <38MHz, which is probably not a good
idea for an LO that produces frequencies up to 40MHz and which is
already struggling at the high frequencies. Replacing the 470R with
100R raises the corner to 160MHz, which is perfectly fine.
This applies to the revision above, with the new 100R right in series
with the IC pin. If this low value were used as a plain
replacement for the 470R R508 then it would probably make things worse.
'No Signal' condition
From earlier observations, it was apparent that there was never a 'no
output' situation, since the squarer self-oscillated at a low frequency
no input and produced a corresponding square wave output. It happened
for Glenn VK3PE in just the same way; here is his 'scope trace at pin 6
of the squarer with no LO signal:
I have suggested implementing an "RV501
Mod" due to inability to adjust for a 50:50 duty cycle with
the original configuration. Because this no longer uses negative
feedback from output to input of the squarer in order to provide bias,
the unstable feedback mechanism that causes the oscillation with no LO
is absent. The output sits at either a high or low static logic level
in the absence of LO (for Steve G7WAS it is a high level).
This leads me
to believe that (for my STAR at least) the official modifications that
a.c. couple the squarer to the buffers (CSQ1 and CSQ2) are not needed,
since there was never a condition of 'no signal from the squarer' and
so the XOR
outputs on pins 8 and 11 could never see threshold inputs, which had
apparently caused overheating for some people and was the reason for
the change. None of the squarers for which I have measurements provides
such threshold output with no LO input. However, there was no
noticeable problem as a result of leaving these components present, so
I retained them. The AC86 input protection diodes on pins 10 and 12
behaved as intended and d.c. restored the coupled signals.
It is worth a mention that not everyone has had success with the a.c.
coupled buffers that drive the bus switch inputs.
These buffers are the remaining two XOR gates in IC503, on pins 8,9,10
and 11,12,13 with the lower numbered gate strapped to be non-inverting
and the upper strapped as inverting, by taking one input pin to Gnd or
Vcc in each case. The AC86 has the same specified propagation delay in
both configurations, making it ideal as a single-ended to complementary
The a.c. coupling 'official mod' was introduced in order to avoid these
sections over-dissipating when fed with a threshold level from the
squarer part; the pull-up/down resistors on pins 12,10 ensuring a
logic level if there is no alternating signal provided by pin 6.
The chip's input protection diodes serve to d.c. restore the a.c.
coupled signals when they are present, to make it all work. I already
mentioned that my own squarer self-oscillates at a low frequency in the
absence of input, and does not produce a stable 'threshold-voltage'
level on pin 6, but it may be that some constructors have
experienced such a static level.
Others have fitted the CSQ modification, only to find that their
buffers then do
not work correctly. Bart Schrijver has had this trouble (he used a
74HCT86 rather than 74HC86 XOR). Bart says:
"I found on both of mine I had to add a 3.9k resistor to ground from
pin 12 to make that arm switch. The other arm switches fine. This
circuit also suffers from asymmetries, I think due to the logic
switching levels that do not happen at mid rail. The suggested
modifications, which add a resistor and capacitor may make things
worse. In my PICASTAR I used the 74AHCT86 versions which may be
worse in this respect. I could not find the specified AC version, since
these are becoming obsolete."
On the ComboBoard, Glenn has made provision for a resistor to be added
by others who have this problem (RSQ4).However, the proper answer is
not to try using the 74ACT device in place of the 74AC part.
I suspect that the obsolescence of the 74AC part that Bart reports is
because the part number he used is that of a 'lead-enriched' part; all
of which are now replaced by compliant lead-free parts with
corresponding distinct part-name suffix.
The eventual drive waveforms from the 74AC86 pins 8 and 11, as shown on
my 100MHz oscilloscope looked as good as could be expected. I used a
short earth-clip lead, but the perturbations due to it are clearly
visible on both traces.
This is the squarer output on 30m band setting
And below is the same measurement on the 10m band
The edge rates are similar to the 'scope rise times. Note that the
"X10 MAG ON" button is pressed, so the timebase is 10ns/div on the 0.1
microseconds/div timebase setting. The trace shows a rise-time of
around 2.5ns; the 'scope rise-time is "less than 3.5ns". I
wish I had a better 'scope - and a cleaner one! The rise & fall
times of the signal are therefore 'very
fast'; less than 2.5ns!
You have already seen the waveform
obtained by Steve G7WAS. Steve's indicated rise and fall times are
about 3ns. No doubt his scope also has probes with limited bandwidth,
so his rise and fall times will be considerably less than 3ns also.
The commutation 'feathers' due to VHF instability at the signal
transitions were exacerbated by the layout of the PCB.
Peter's original layout has very short track on the input
(IC503 pin 1) and no other signal tracks run close. But Glenn's layout
introduced significant length at the input, as well as close proximity
to the output signals, which must increase the
possibility of instability. Note that Glenn used the same layout for
all his PCBs ('bricks' and Combo).
In the images below, the upper layout (Peter's original PCB) has very
short tracking on pin 2, isolated by R8 and R26 immediately and with no
other tracks adjacent. The output on pin 6 is well away from the input
pin, partly because coupling capacitors are mounted over the chip body.
The lower layout is from my own ComboBoard (Glenn's layout) before any
modifications. I have
coloured two tracks for clarity. It is clear that not only is the track
on pin 2 about as long as it could be, but also that the track to pin 6
(which is the stage output signal) passes close by as it connects to
the following circuitry. Remember that Glenn has run the part numbers
on this section of the Combo from 500, so R8 and R26 on Peter's layout
become R508 and R526 respectively on Glenn's.
The conclusion that I came to is that Peter's original layout did the
things that would assist stability, but Glenn's layout did not.
However, the modification presented earlier to
reduce the parasitic oscillations is easily done on the ComboBoard and
isolates the long track (red in the picture) from the chip input, which
is what is needed. It is easy to do on the board and is also easily
reversible. There is no easy way (you could consider cutting the track
and using wire for a different route) to avoid the track from pin 6
(orange above) passing under the chip and therefore close to the pins
and beneath the die.
Measurements of sensitivity
Glenn VK3PE has kindly made measurements of the minimum LO level that
he found necessary in order to produce a useful output from the
squarer. In these measurements, a lower input level requirement is
He did not use a complete Picastar, but made up a test PCB containing
little more than the squarer plus output buffers:
Glenn then measured the LO input level (from a signal generator) that
in order to give clean output signals with no observable parasitics or
The reduction in LO level needed in order to obtain a clean output is
noticeable. At higher frequencies there is still a bit of a kink, but
in general it is better behaved. The smallest LO level needed for the
original is 4.5dBm; for the revision is 3.5dBm.
Although I don't have data to support it, Glenn achieved a maximum
frequency of well over 100MHz with the revised version ("Change R508 to
0R and add 100R right at Pin 2" in the plot above), still with less
Do the mod; it is simple and is easily reversible should you wish.
Bob's Combo with R508 as a 0R link and
a 100R 0603 at the lifted pin 2. Lots of blobby soldering as the result
of many experimental changes!
Recommended Changes to ComboBoard
For the pin 2 mod:
- Lift IC503 pin 2 carefully from the PCB pad,
- Insert a new 100R 0603 resistor between pad & pin (0603 fits
- Short R508 either with wire or a '0R link'.
For the RV501 Pot mod:
This is more difficult to perform.
You can now adjust RV501 for best symmetry of the squarer output at pin
6, on the band of your choice.
- Isolate one end of the track, leaving the other end at Gnd,
- Wire the isolated pin to +5V,
- Check that the wiper goes to R529 (this may require a cut &
- Remove R527,
- Verify that the voltage measured at R529 is now adjustable
between Gnd and 5V.
- Finally, adjust RV501 approximately to mid-rail as a
It is OK to link the wiper to either end of R529, whatever is
convenient (see schematic above)
Following this investigation, Glenn and I devised and tested several
layouts. One of these produced excellent results, with good
sensitivity and freedom from instability on the transitions. The
operating frequencies easily extended well beyond the range that would
be needed. Because the PCB changes, these are not suitable for
modifying the Combo (unless Glenn produces a new ComboBoard!). I
have detailed them as
Capacitively Coupled Drivers
The output of the Squarer is capacitively coupled to the two XOR buffer
stages that produce the true and inverted drives to the Bus Switch
device that is the H-Mode Mixer. These were provided (CSQ1 and CSQ2) in
order that the buffers do not sit with their inputs at threshold in the
absence of LO input. I had found that this did not happen; my own
squarer oscillated at a low frequency with no LO input and still
produced proper logic levels. Others
have found the same. Nevertheless,
rather than removing (shorting) the capacitors, it is OK to
retain them. The
Appendix looks at some considerations.
It was suggested to me that the XOR used in the squarer and for the Bus
Switch buffers does not have adequate slew-rate. I studied this in an Appendix and concluded
that even at worst-case it is perfectly adequate. From the various oscilloscope traces you can see
anyway that the rise-time achieved is less that 3ns. What more could
Appendix: More about
CMOS gate thresholds
The saturated swing of any logic gate output or internal intermediate
stage, being an amplified version of the input, has
slew-rate, depending partly on the input amplitude and the stage's
(which is usually between 10 and 100 for a single CMOS stage of those
within one XOR gate - such as one only of the pairs of FETS labelled
'p' and 'n' in the circuit below). During
this slew, both the P & N-channel FETs of the stage will normally
drawing a fairly large current through themselves from the supply to
ground. This may cause instability, perhaps by the current in the
ground bond-wire causing the source of the N-channel FETs to move
slightly positive; equivalent to a feedback to the input (which is
between the chip input pin and an external ground). This can cause
instability during this time, often at VHF or UHF, and is caused by the
of the chip metallisation and bond wire. In normal digital operation,
the input slews very rapidly through this threshold, but our incoming
sine wave has finite slew-rate...
In our squarer, the output of this first stage then feeds the second
(the XOR has four
CMOS stages in cascade per gate) and the external connection between
pins 3 and 4 feeds it on to the next gate and thence to the output on
Obviously, as more such gain stages are cascaded, the later stages tend
to switch more suddenly because the slew-rates get progressively higher
(for our rather slowly slewing sine-wave input). At some point on the
many stages are switching simultaneously and rapidly, all gulping
supply current as they do so. That supply current all flows in common
ground paths (such as the chip bond wire) and yanks up the internal
ground relative to the external (PCB) ground. This can be oscillatory
at VHF/UHF due to ground inductances, and represents a signal
effectively between the input (pin 2) and it's N-channel source, which
happens just as the FET pair is in the linear region and has gain...
The result is oscillatory feedback until the input signal moves the
input pin away from the linear region of the stage. The more complex
the gate, and the more sections within the chip that are involved, the
larger the ground perturbation will be, hence the more likely is
instability. This was the source of my observed 'feathers' on output
transitions. Since it is happening within a sensitive part of the
receiver, it can give rise to all manner of squeaks and squawks. The
best way to minimise the time spent with the input stage in the linear
region is to drive it with a very fast-slewing signal. Obviously this
is what a logic circuit does, but we are using a sine-wave and can only
make it slew more rapidly through threshold by increasing the
amplitude. This is why the amplitude corresponding to +7dBm is needed
at the input. Even the 1.44vpp is not over-generous - if the first
stage has a voltage gain of 10, then for the stage output to saturate
(and therefore have no gain to input changes) then the stage must see
at least a 0.5V 'chunk' of the sine-wave input; you can work out how
long the input stays within this +-0.25V window (and hence is
I have no internal circuit for the 74AC86, but below is the circuit of
a single XOR gate within the TI CD4030, a similar part (but different
pin-out and speed; it's a rather old part). As you can see, it is a
complex gate with oodles of PN 'gain stages' per gate!
Philips very kindly give even more insight into the use of an
unbuffered CMOS inverter in
the linear mode (just a single stage per section), even showing how it
used as an amplifier or oscillator. The most relevant items for us
right now are the gate transfer characteristics, which I reproduce
You can clearly see the single PN pair that is one inverter.
Below is the transfer
characteristic of just this single stage:
The gulp of supply current (up to 12mA) as the input passes through the
threshold is painfully apparent. The slow rise and fall of current as
the input sweeps from 0 to Vcc is the result of each of the FETs
progressively drawing more current through its saturated partner. At
the point where the output passes through mid-rail they are each
equally enhanced (and the current is at maximum).
Multiply the above peak current by the number of stages in an XOR gate
to get a very rough idea of what the peak current drawn by that gate
might be. We have 4 XOR gates cascaded, nominally biassed at threshold
(peak current) and each gate contains 4 active PN pairs (per pin)
so we could have 16 of the above elements all drawing their peak
of 12mA simultaneously through the metallisation and bond-wire; 192mA
Circuit designers place a low-ESR capacitor as directly between the
supply pins of the chip, in order to provide this gulp of current so
that it does not flow through the power tracks and affect other
It also hold the chip power pins at a reasonably steady voltage in the
inevitable presence of supply-feed inductance. But not surprisingly
there is no
such capacitor within the IC, on the die, so the gulp of current does
flow in the impedance of the die metallisation, bond wires and pins
also. At this time, the supply voltages on the die can vary
considerably. Remembering that the ground impedance is in series with
the LO input signal, this transient can momentarily alter the apparent
input signal and give unwanted VHF feedback. This is in addition to any
output signal fed back by capacitance, and may produce transient
instability (modern CMOS logic devices have very high internal
I wondered if Philips' data-sheet for their 74AC86 showed such helpful
characteristics of the supply current vs input voltage. But they
clearly don't think anyone would use it in a manner where this would be
important (only as a digital gate).
Appendix: XOR Output
It has been suggested to me that the 74AC86 chip has inadequate rise
and fall times for use on the 10m band. When this was suggested on 'the
response was to 'build it and see how it works', which is not entirely
So let's see.
For reference, I am using the Fairchild 74AC86 data sheet dated
Revised February 2005.
The input-to-output propagation
delay affects symmetry of an output
when fed by an input. For this device the range of both high-low and
low-high delay is 1.5 to 8.5ns at Vcc=5V, with the typical for
both being 4.5ns. This looks good. If they are always the same (e.g.
both at minimum) for a given device, this is not a source of
distortion. It is likely that they will be the same for a given chip
(which is fortunately the one we used [sad attempt at humour, sorry]).
Sadly, for this data-sheet, this is the only dynamic characteristic
specified. I guess we will need to look at either another
data-sheet, or at ACMOS family characteristics.
The Fairchild 74AC Family Parameters data sheet "FACT(tm) Descriptions
and Family Characteristics", November 1988 Revised January 2000, gives
some generic parameters. On page 13 is a pair of curves showing rise
& fall times with various load capacitances at a supply of
5V, for a normal gate (not a bus-buffer). This shows that, with
10pF load, the rise-time is about 1.8ns
and the fall-time about 1.4ns. Rise-time increases to just over 2ns
with 20pF, while fall-time remains below 2ns. Of course, these are for
a typical device at Vcc=5V, 25C, but they are the best we will
find. Here they are:
Remember to look above at the curve for FACT AC, not FACT QS.
In the Picastar design, the input capacitance of the pairs of bus
forming the H-mode mixer is isolated somewhat by the small (56R)
resistors in series with the drivers, R501 and R502, which can just be
seen in the scrap circuit well above. The
input capacitance of a single
Fairchild bus switch is typically
3pF (no limits given), so two in
parallel give 6pF. If we allow a couple of pF for the PCB track and a
bit in hand, we get 10pF. This is at the low end of the curves for
AC device rise/fall times in the graphs above and will give less than
2ns rise-time. The
resistors will add some, but with a time-constant of half a ns (56R,
10pF) it should not be much (the eventual value is 'root sum of
squares' of the rise times, which will be a tad more than 2ns).
I would certainly expect the bus
switch inputs to see a signal
rise-time of around 2ns to 2.5ns.
With my 100MHz
'scope and x10 probe I measure around 2.5ns on my own STAR, but
bear in mind that this is not only below the specified maximum
'scope rise-time, but also I have the extra capacitive load of the
'scope probe present. Nevertheless, I'm happy to call it 2.5ns drive
rise-time and fall-time. It isn't more than this. Steve G7WAS also
measured this with closely similar results.
At 10m the LO is roughly 40MHz, so a half-cycle takes 12ns.
Within this time, a rise-time of 2.5ns is a small proportion.
Bear in mind also that the bus switches have internal drive buffers, so
actual part of the rise-time over which switching occurs within
the bus switch is much less than the 10% to 90% transition that is rise
time. It may
actually happen over the central 1V or less of the waveform, which
takes only about half a ns to slew. Worrying about the slew rate of the
74AC86 outputs is therefore not something we need do.
Also, provided that the rise and fall times are similar, the receiving
device (bus switch input for us) will see both edges occur slightly
later than the transmitting gate (the 74AC86) began sending it - but
these compensate and the resulting width distortion is small. It
appears as a slight signal delay rather than width distortion, so long
as the waveform has time to complete the logic transition before the
next transition occurs.
This input slew (through logic threshold) is not the same as the
operation time of the bus switch, which has its own delays and
internal slews, but that's another story (the FST3125 spec is 1ns to
5ns enable time, and 1.5ns to 5.3ns disable time, but it isn't so easy
to measure and is something we should simply live with).
If, on observing this waveform, a significantly slower slew is seen,
you should ensure that the measuring equipment is entirely capable,
with adequate 'scope and probe bandwidth and a properly compensated X10
probe used with near-zero length tip & ground connections.
From this, therefore, I believe that the drives to the bus switches
have perfectly adequate rise-time and fall-time.
coupled buffer stages
The high-numbered pin gates (pins 8 to 13) of the 74AC86 are the ones
used to drive
the bus switches that constitute the H-Mode Mixer. Both are driven with
the same output of the squarer, from pin 6. One gate is strapped as
other as non-inverting, thereby producing the complementary drive
waveforms required for the bus switches. This arrangement is good,
gates are on the same die and will therefore have closely similar
characteristics (mainly propagation delay and output drives) within the
worst-case specification. This way we get accurately matched
complementary signals, needed for best mixer operation.
In the past, an 'official modification' was introduced which a.c.
couples the squarer to each of the buffers. A pull-up or pull-down
resistor (as appropriate for 'anti-phaseness') gives a definite
'no-signal' condition, and the chip input protection diodes are used to
d.c. restore the coupled drives and keep them within the input range
(the components are CSQ1, CSQ2, RSQ2 and RSQ3).
This modification was intended to help prevent over-dissipation by
ensuring that all 4 gates did not sit at input threshold in the absence
of an LO signal. On my own build (and at least three others where I
have been given results) this did not happen; the squarer
self-oscillates at a low frequency and would provide good logic-level
drives to the output buffers in this case, but just because I don't
experience it doesn't mean it can't happen (it may actually be that
each stage internally oscillates at a high frequency, with internal
non-linearities producing a near d.c. output level, since these gates
are complex and unlikely to sit stably at threshold).
Given that the a.c. coupled waveform is DC-restored, it must exceed the
conduction threshold of the diode (the input protection diode). For
each gate, this means that the resulting signal will swing one way
beyond the rail (for diode conduction) and the other way
correspondingly less than the rail. For a 74AC86, the clamp diode will
conduct at around 0.6V to 0.9V (it is an esd clamp, not a precision
Bear in mind here that RSQ1 loads the high level of the squarer output
(pin 6) and causes a shortfall of 0.3V in the high level out.
One buffer will therefore see an input signal of (Vdd-0.9-0.3)V to
the other (Vdd+0.9V) to (+0.9+0.3)V.
The logic thresholds for 74AC86 are between 30% and 70% of Vdd; for a
5V supply this is 1.5V to 3.5V. The d.c. restored signal comfortably
crosses these points, so all devices should work.
It is useful to consider the 74ACT86
The logic thresholds for 74ACT devices are 0.8V to 2.0V irrespective of
Vdd (limited to 4.5 to 5.5V). We saw (above) that the logic swing after
d.c. restoration on one driver could be (Vdd+0.9V) to (0.9+0.3)V - this
driver with the resistor taken to Vdd, of course. Now the swing
is not comfortable, since the low level after the d.c. restoration is
1.2V, which is not cleanly below the low threshold (0.8V) of the device
and will probably not produce a (satisfactory) output signal
on that driver. The other one will be fine!
On the schematic is an optional resistor RSQ4, which reduces the aiming
voltage of the pull-up RSQ3 and therefore modifies the clamp levels
slightly. In the limit, if it were made equal to RSQ3 then an AC device
would nominally be linearly biassed again, which is what we are trying
to avoid, so it will be made larger than this - unless we have used a
74ACT86, with thresholds
between 0.8V and 2.0V. This resistor will then
better ensure that the low period of the d.c. restored signal actually
crosses this rather low threshold.
Since the 74ACT86 is not good for either the squarer or the buffers,
avoid it. It is a reasonable substitute for the 74AC86 when used as a
general logic device, but not for these highly threshold-centric uses.
Physical Layout Changes to Squarer
Whilst musing on the squarer, some possible physical improvements
- The first thing is peculiar to the ComboBoard layout. A track on
the IC side of the PCB passes from the squarer output and runs beneath
the body of the IC to eventually connect to the capacitors CSQ1 and
CSQ2. This track carries an inversion of the input and passes close to
the input pin (and closely below the package die). When the input
signal begins to cause a logic transition on this track, some of the
edge energy is bound to feed back to the input (in anti-phase to the
input that caused it. This not only opposes the input signal, but is
also a known cause of high-frequency oscillation. A better
physical arrangement is needed.
- At present, the input to the XOR is on pin 2, with pin 1 as a
supply rail setting the stage as inverting. Energy appearing at
transition of pin 3 (the output of the first stage)
is fed back to the input by the close proximity of these pins and the
chip bond wires. This feedback, being in anti-phase with the
LO signal, opposes the very input change that causes it. This is a
source of instability. By swapping these pins, the input (now on pin 1)
is screened from the first gate output on pin 3 by the rail now
connected to pin 2. This happens even inside the device package, with
the bond wires rather than outside proximity, and probably also happens
on the die. By arranging the pins like this, far less of the pin
3 signal is fed back to the input. This reduces the tendency of the
stage to be unstable. In addition, a ground (or supply) 'Guard' between
this track and the low numbered pins could be used in order to minimise
fed-back signal. This is standard practice.
- Then the real humdinger hit me. At present, the first stage is
configured as an inverter and the second as a non-inverter. The
configuration is done by connecting the second XOR gate input to the
appropriate supply rail in order to define the signal pin as inverting
or non-inverting. The use of the first stage as inverting automatically
gives an environment likely to produce VHF or UHF oscillation at
transitions due to feedback, both on and off-chip. Why not swap
these 'inversions' and let any such feedback cause the short-term
reinforcement of the input, rather than opposing it? This was worthy of
The Full Change
This change retains the better screening of the revisions above, but
takes the feedback that was anti-socially opposing the input signal,
and turns it on its head.
Over my cornflakes, I was musing idly on the fact that the stray
capacitive negative feedback acts against the input transition, and
wished it were positive feedback (hysteresis) so that the circuit would
'snap' over to the new condition instead of wallowing through the
threshold. Then I realised how easy it is to arrange this!
In the original design, the first gate is arranged to be inverting; the
second non-inverting, to give the required overall inversion.
But why not reverse this - make the first gate non-inverting and the
second inverting! This is so easy with the XOR function, since it
simply means swapping the static voltage levels on the 2nd pin of each
provided that the feedback was predominantly within the first gate
(which seemed likely after doing all that screening), the negative
feedback that fights the switch-over and causes transient instability
would become positive feedback, reinforcing the switch-over and
defeating instability, so long as the time-constant lasts long enough.
And we can always add a tiny
capacitance to increase the hysteresis effect!
This onwards is cut
& pasted from the original page and probably needs changing!
A few calculations later, it seemed well worth trying:
The amount of feedback we get from strays depends, naturally, on the
For calculation, I assumed that there is a capacitance to ground on the
input pin of typically 4.5pF due to the XOR gate (Philips data-sheet)
and maybe another 1.5pF due to the PCB pad and the connection to the
100R input resistor; a total of 6pF.
The feedback capacitance is far more nebulous, but my wild guess is
is 0.1pF with the revised layout. This forms a capacitive divider, so
that the output step on pin 3 (of 5Vpp) appears on the input as a step
of 5V *
(0.1pF / 6.1pF) which is 81.96mV
This then decays due to the 125R (100R input resistor + two paralleled
50R source resistance), which has a time-constant with the 6.1pF
only 75ps. The deliberate LO a.c. coupling has a much longer time
constant and does not affect the result.
The effect is therefore to provide an 81mV step feedback as the first
gate responds to the change of LO signal (the sine wave transition into
gate threshold). This step is in phase with the LO signal and
reinforces it, causing the output to 'snap over'.
Within 75ps the reinforcing feedback has decayed by 60% (an exponential
decay of one time-constant); by three time-constants it has become
Let us check that the feedback works in our favour and has decayed soon
enough not to upset behaviour:
The rate of change of the incoming LO sine wave as it passes through
the gate threshold is approximately that of a sine wave passing through
the zero-crossing, at which point it is slewing most rapidly. The
approximation is due to the possibility that the adjustment
potentiometer R has been used to offset the automatic threshold
Let us assume that the input is a 50MHz sine wave, which is the highest
frequency we might intend to use.
The rate of change of this sine wave at the zero crossing is
3.92V/ns * Vpk. For our nominally +7dBm LO input, the amplitude is
1.414Vpp, 0.707Vpk, giving a slew rate at the zero crossing of 0.707 *
3.92V/ns = 2.8V/ns (this assumes that the tangent to the zero-crossing
waveform is very close to the actual sinusoid during this time, which
is a reasonable assumption for a tiny voltage change).
So, as the capacitive hysteresis decays to 40% in a time-constant of
75ps, so the LO signal will have moved by about 200mV, reinforcing the
logic state. Thereafter the LO sine wave will overdrive the input until
eventually it crosses the zero-value 'the other way' and it all begins
At lower LO frequencies the slew rate through the zero crossing is,
naturally, slower; this might mean that the input sine has not moved
far enough to hold the stage in saturation after the hysteresis has
decayed, but it will always be better than before.
To check that the hysteresis due to stray feedback capacitance will not
prevent the subsequent zero-crossing being seen, we can see if the
feedback effect is over within the prevailing half-cycle at 50MHz; this
is 10ns duration. Our capacitive feedback had a time-constant of
75ps; after 3 time-constants it will have decayed to roughly 1% of the
original step, i.e. from 82mV to 0.82mV, which is wholly
insignificant compared with the input of 0.707Vp - and after 10ns (an
input half-cycle) it will have decayed for 133 time-constants and will
be totally negligible, which is excellent.
The above calculations show that there is a likelihood of obtaining
really excellent results, with no possible disadvantages. As soon as
the incoming LO sine wave 'tickles' the circuit enough to start the
output shifting, the stray capacitive feedback reinforces the change,
causing the output to move more rapidly - it snaps over to the new
This is in contrast to the original behaviour, where the negative
feedback opposed the LO
signal transition once the gate output began to change state, causing
the whole commutation to take longer and promoting VHF oscillation
until the incoming sine wave provided sufficient drive to swamp it.
So Glenn made further alterations to the layout.
This time he also did away with the connection beneath the IC taking
the squarer output from pin 6 to the Official Mod capacitors on pins 10
& 12 in order entirely to do away with the track beneath the IC
(another possibility would be to run it on the opposite side of the
PCB, but this would result in a break in the ground fill on that side).
As you may have gathered in earlier parts, I did not ever see a stable
threshold state that would make the extra components worthwhile.
Similarly, Glenn has built this circuit several times and has also only
seen the low-frequency saturated oscillation that I mentioned earlier.
However, in recognition of this mod, Glenn suggested that the caps
should be fitted over the IC body as in the original mod and as is done
on the mixadaptor for the second mixer; using plain wires (direct
connection) first in order to see if the
capacitors were needed.
An 0603 pad-pair connected to the IC pin 3 (output of non-inverting
first stage) and pin 1 (input directly on the pin) would also permit
the addition of a high-value resistor (several Megohms) to apply
deliberate but small d.c. hysteresis if needed, or to be a place to
solder two short pieces of wire to increase the capacitive feedback if
this seemed advantageous. In the event, neither was used.
works wonderfully well.
There was no sign of any disturbance on the rising or falling edges of
the output, unlike the earlier attempts which all showed 'fuzz'. In
addition, the sensitivity (or, at least, the smallest signal which gave
a clean output) was improved considerably.
Of course, there is still an input level below which the circuit
produces a rubbish output, but this is inevitable and only differs from
the original circuit in that it still 'snaps' from state to state
rather than producing frantic self-oscillation.
This, then, represents the most sensitive, least unstable configuration
and is possible because we use an XOR gate and can readily make the
stages invert or not by the static d.c. level on the second input. The
only parts of the circuit where inverting feedback can occur is on the
die or from pickup on the input of output signals.
Of course, this change in particular really needs proper PCB
implementation, so it is not a ready mod for existing boards.
Glenn suggests the possibility of a small 'add-on' PCB in the manner of
his test layouts; this could replace the present squarer entirely.
Glenn's results with and without the modification coupling capacitors
showed no difference in any practical respect. With no LO input, the
circuit oscillated at low frequency (as it always seems to do); with no
coupling caps the drives to the bus switches follow this. But with the
caps present, the short time-constant differentiation means that the
buffers transit slowly through their thresholds in this condition. I am
more concerned that, at this time, those stages may oscillate or at
least draw supply current through the PN pairs, either of these things
possibly affecting the input (which of course shares the same ground
bond-wire and possibly some die metallisation). So it seems best to
link these signals directly, without the CSQ additions - Glenn simply
shorted the capacitors that he had fitted above the IC to do this!
The inevitable conclusion that I reach is in several parts:
Having ploughed through the words, you will want to see some pictures
of these improvements.
- The original XOR pin allocation puts the LO input on an adjacent
pin to the output, which gives maximum unwanted -ve feedback.
- The layout of Glenn's ComboBoard (which is the same as his
individual PCBs) runs the squarer output track beneath the IC, close to
the input pin, also giving unwanted -ve feedback.
- These feedbacks can be greatly reduced by feeding the LO input to
pin 1 of the XOR rather than pin 2, and by improving the ground-plane
screening beneath the IC.
- These changes will not affect the sensitivity of the circuit to
LO signal, but will reduce the parasitic oscillation that occurs on the
output transitions ('fuzz' on the edges). This appears to be a sensitivity
improvement because less signal is needed in order to get a clean
- The original gate configuration, which used the first XOR stage
as an inverter and the second stage as a non-inverter, fortuitously
provides the worst condition for stray feedback and promotes
instability in the squarer.
- By reversing the order of the stages to make the first gate
non-inverting and the second inverting, the overall inversion is
maintained but the main feedback mechanism swaps from negative to
positive feedback. The resulting capacitive hysteresis gives a sharp
switch-over of state instead of oscillation at the transition.
- The lack of VHF oscillation caused by the original stray negative
feedback means that less or no edge-parasitics will occur with a much
- The much lower input-pin capacitance and reduced series resistor
that is now possible permits the operating LO frequency to be very much
higher, with reasonable LO requirement and no sign of VHF instability
- The circuit now operates well at frequencies in excess of 100MHz
with LO level of around +5dBm. The original circuit needed over +5dBm
at 80MHz in order to begin squaring and was unstable at this level,
with parasitic oscillation on output transitions.
The results below were obtained by Glenn for each of the above
configurations; he has kindly allowed me to reproduce them here.
The principal inverting configurations are as in the picture below.
These all require a new PCB layout and are not possible as
modifications to an existing PCB.
Clockwise from the top these are:
These, in reverse order, represent the three principal versions where
the first XOR gate is inverting.
- Signal input to pin 1 of XOR, improved ground screening, short
- Signal input to pin 2 of XOR, improved ground screening, short
- Signal input to pin 2 of XOR, original (Combo) layout, long input
track on IC pin 2!
The final design changes the order of the inverting and non-inverting
XOR sections to non-inverting, inverting. This retains the identical
overall inverting configuration, but local stray feedback in the first
stage and associated tracking is now +ve rather than -ve feedback. This
provides regeneration that causes the output to change state rapidly
once the input threshold is reached, rather than the original
degenerative feedback that not only opposed the input (resulting in
reduced slew-rate) but also provided the mechanism for VHF/UHF internal
oscillation during the transition. Because any coupling capacitance is
small, the regeneration does not persist long into the LO half-cycle.
The photo below is of the fully modified test-layout, now with
(stray-dependent) hysteresis and with the squarer output no longer
passing below the IC but with capacitors taken above it. The capacitors
have been linked out using wire, with no ill effect. The ground-plane
is cleared from under the input-pin (XOR pin 1) and 100R resistor end,
in order to minimise node capacitance.
This is the final test-layout. There may be small improvements
possible, but this is now unlikely.
None of the physical changes
described in this section can be done properly on an existing PCB, so
they are not things you can try easily. That is why I have kept this to
an appendix. If Glenn ever produces new artwork, he might be tempted to
incorporate some or all of these changes - but there is no reason for
this. In any case, the easy modification to the original layout
(putting 100R right at the pin, as described a lot earlier) gives
pretty good results and is painless.
So how does it perform?
Glenn kindly performed more measurements on his home-made PCBs.
Glenn's graph shows, as before, the input level (dBm) necessary in
give a reasonable output - a lower input requirement is better:
Note that these measurements show an odd shape for the swapping of pins
1 & 2 on the XOR, not at all what we might expect. Glenn later
repeated all these measurements and included one without the pot RV501
(still in the original 'RTFM' configuration).
The "100R at pin 1" measurement is for the modification of a standard
ComboBoard as described earlier.
"Bob's mod" is the swap of inverting & non-inverting gate functions
as described above. In addition, the track lengths on "Bob's mod" and
"Swap 1-2" have been reduced as much as possible, and the ground plane
beneath pin 1 (now the input) and the resistor connected to it has been
removed in order to minimise the input node capacitance to ground.
The final set of measurements are shown below.
These include one with the original layout having the 100R at the
(lifted) input pin, but with the original resistor still present - this
is just for information and does not represent a useful configuration.
Interestingly, sensitivity and flatness of slope are both very much
better in the test without the pot RV501 fitted.
None of the results that I have presented show the highest frequency
that the revisions can achieve. Here is something for the "Bob's Mod"
inversion-swapped layout at up to 70MHz:
There is no significant reduction in sensitivity, which is encouraging.
Furthermore, Glenn was unable to see any sign of 'feathery edges' at
the output; these are a sign of VHF instability at the transition point
and were visible for all the "unswapped" versions.
From this, it seems as if the fully revised squarer will operate at
over 70MHz with less than 4.5dBm of LO. In fact, Glenn recalls that
this version operated at well over 100MHz without any problems. Maybe I
can persuade him to see what the maximum frequency of reasonable
operation is with, say, +7dBm of LO... Not that the MR or front-end
will support this, though!
Glenn VK3PE has kindly measured the board response again, for
frequencies up to
150MHz. Also, he patiently explored the strange slope around 100MHz
(probably a resonance) by
taking smaller frequency steps:
These tests were all performed with the original feedback biasing
configuration (RV510 not re-deployed between supplies and R527 still
providing feedback). For the test above RV501 was not fitted, but
otherwise the configuration was the same. The re-deployment of RV501
and removal of R527 is recommended, however, since it permits
adjustment of mark:space for XOR devices regardless of their threshold
voltage. This also provides maximum input sensitivity whilst permitting
production of a square-wave.
Please bear in mind that the squarer benefits from being given the
possible (so long as the input protection diodes of the XOR don't
conduct). All the results presented here are for the smallest LO level
that gives good output squaring as seen on an oscilloscope. They do not
represent the level that you should use!