PICASTAR Second IF (Receive path)

This is a part of the overall 2nd IF study and covers only the Rx path.


As you have already seen, my attention was grabbed by the PI pad that precedes the common-base amplifier TR603. Here is the way things progressed:


If you decide to use any of the information here, you will make your PICASTAR non-standard. Even if you wish to do the changes on a 'new-build' STAR, please build it first using all the standard build information, with no changes from the published design. Also you need to calibrate it using all the excellent BASIC programmes, to verify that it works correctly, before you modify it. This is what I did myself.
If you do not 'RTFM' (read and use all the PICASTAR documentation in the Yahoo! Groups Pic-a-Project group before you modify your build in any way, then no-one will be able to help you to get your own build working. You must join this group in order to obtain (and be permitted to use) the design information that you need. If you then need help (with an un-modified STAR) you will get it by posting your problem on the picastar-users group. If your STAR is modified in any way, then the very helpful people on the picastar-users group will probably not be able to help you.


The following points are wrong with the design of the Second IF Receive Path:
The analysis and correction of these is described in the sections below

Common Base Amplifier

First, and starting at the output in time-honoured analogue design way, let us look at the common-base amplifier stage. A circuit simulator could do this, but it's fairly easy to do as a 'head job' and far more satisfying than always relying on software!

D.C. conditions

The common-base amplifier stage is powered from the regulated +10V supply. The d.c. biasing presents a base voltage of 2.87V from the potential divider R632, R614 (8k2 and 3k3), (initially assuming insignificant base current) which results in an emitter voltage of roughly 2.27V across the emitter resistor R611 (2k7). The emitter current is therefore about 0.84mA. Since the 2N3904 has a specified d.c. current gain (hFE) of >70 at 1mA, which is close to our operating current, the static base current will be no more than (0.8mA / 70), which is 11uA. Assuming this as a load on the base potential divider reduces the base voltage from 2.87V by flowing from the effective parallel value of the two resistors of 8k2 and 3k3, which is 2k35. The drop in base voltage is therefore less than 0.026V, which is negligible (especially considering my arbitrary use of 0.6V as the base-emitter offset!).

The emitter current therefore flows almost in its entirety in the collector, which has a load of 5k6 (R620) and which feeds an op-amp configured as a voltage follower (therefore presenting no significant load). The voltage drop in the collector load is therefore 5k6 * 0.84mA, 4.7V drop, setting the collector voltage at (10 - 4.7)V = 5.3V

The transistor is operating with a Vcb of (5.3 - 2.27)V = 3.03V which, whilst maybe a scrap low, is still workable.
We therefore have the following (nominal) d.c. conditions on the common-base amplifier:
Vb = 2.87V
Ve = 2.27V approximately (temperature dependent)
Vc = 5.3V
Ie = 0.84mA

A.C. conditions

The only thing we need here is the input resistance of the circuit, which is the load to the PI-network. This is not really an 'a.c.' condition, but at our low frequencies it will suffice. It is really the dynamic input resistance.

For a grounded-base amplifier, the input resistance is low and is approximately equal to re, the 'intrinsic emitter resistance', which at d.c. is roughly (26R / Ie[mA]) plus the reflected base-circuit resistance (Rbase / hFE). This gives us (26R / Ie[mA]) + (Rb / hFE).
Using the values calculated above, this gives:
(26R / 0.84mA) + (2k35 / 70) = (31) + (33) or approximately 64R.

This applies at d.c
. For a.c. we need to consider the base decoupling capacitor.
The impedance on the base above 700Hz is very low, so we can use Rb = 0 in the calculation (in reality there is also intrinsic base resistance, but it is very low), leaving only the intrinsic emitter resistance plus a small amount for other physical resistances.
The input resistance at 15kHz will therefore be just above 31R.

But - the emitter d.c. voltage is isolated by the blocking capacitor C633 (220nF). This MUST have low reactance at the 2nd IF in order not to attenuate the signal fed to the emitter.
The 2nd IF is 15kHz, and the reactance (Xc) of 220nF at 15kHz is 48.23R - this is way excessive, being higher than Zin of the grounded base stage, and will adversely reduce the stage gain if nothing else. We should be looking to have a value of Xc no greater than 10% of the load XL (and preferably a lot less than this) in order to be reasonably clean. The value of 220nF should therefore be increased to at least 2u2 - and since 10u ceramic capacitors are readily available in small body size, this would be better albeit slightly more expensive. Penny-pinching is not sensible, in view of the already high cost of building a STAR.

Farnell lists many 6V and 10V parts; a good choice is a 10V part such as 9402136, from Yageo, at 24p each for 10+. They are a good thing to have in hand anyway... There are many other, suitable parts. For cheaper, 2u2 capacitors consider Farnell 9527702 (Murata 2u2 25V) at £0.107 each in tens, or find something similar, but really the 10uF parts are a Good Idea. In this position, the dielectric type is not of paramount importance, especially if a large capacitance is chosen in order to minimise the effect of variations in capacitance due to temperature coefficient and tolerance, etc.
I will assume that this has been / will be done, since a corner frequency that attenuates the 2nd IF is Not A Good Idea!

Now the PI pad

With a load resistance of about 31R, we can work out the load to the diplexer that the PI pad input presents. Of course, the attenuation can also easily be calculated.
The input load is derived from the series-parallel combinations of the resistors in the network, with the emitter load in parallel with the output resistor of the PI.

Let's do it for the nominal 50R load first:
For the resistors shown (470,100,82) we get an input resistance of 470//(100 + 82//50) if the emitter load were 50R. This easily simplifies to 470//131.06 which is 102.48R. Not even close to the expected 50R.

Let's try with the original input resistor of 82R, just to see...
This gives 82//(100 + 82//50), similarly to before, which is 82//131.06 = 50.44R : That's more like it!

But the amp input is not 50R (by my calc above) but nearer 31R. How does this change things?

The PI input resistance is now 470//(100 + 82//31) = 97.17R : not much changed from 102.48, which is of course one reason for using a pad; it buffers variations in the load characteristics in order to present a more correct load to the diplexer - in this case, an incorrect but buffered load of about 100R instead of 50R.

Again considering the original pad with 82R input resistor rather than 470R, we get 82//(100 + 82//31) which is 49.12R, a very reasonable nominal 50R load.

So far

The signal path is not so good. First, the pad has had the input shunt resistor doctored 'to increase signal level' by increasing it from 82R to 470R. This upsets the impedance at the pad input (& diplexer/filter output), making 102R instead of 50R. A minor benefit is that the 10R on-resistance of the bus switch (with original bias point) becomes half as significant in the total, but it is not what was intended by the modification.

Better is to have a 50R pad of lower attenuation if we need more signal.
82-100-82R in a 50R path gives 12.5dB with 47dB return loss.
150-39-150 would give 6.19dB with return loss of 43dB.
This is a far better way to increase amplitude!

Coupling Capacitors

Then also the series caps are much too small. They all need increasing to at least 2u2.
At present, C633 into the emitter is 220n, Rin is about 33R (hence the pad), so -3dB is at about 22kHz;
Our desired signal is at nominally 15kHz +-3kHz, so we are operating below the l.f. -3dB cutoff. Any variations in actual capacitance due to temperature, voltage and aging of the Hi-K capacitor will make the actual corner frequency unpredictable. In addition, Hi-K capacitors are known to exhibit non-linearity to a signal - the severity of this is maximised when a significant a.c. signal is present across the capacitor as here. Nominally half the signal appears across the capacitor; any voltage-dependent or frequency-dependent characteristics of the dielectric will modulate this voltage and cause distortion. This effect can be minimised by ensuring that only a small signal voltage is developed across the capacitor, so that variations in this due to dielectric behaviour represent a small part of the whole signal. A value of 10uF is good for this and for reducing the corner frequency (which is clearly needed anyway). For more on the choices see the small section on choice of capacitors.

The other 2 caps, CZ3 (1u) in series with C631 (220n) present 180nF, so the -3dB frequency is at 17.7kHz, also above our 2nd IF! This is fortuitously slightly 'improved' by the on-resistance of the bus switch, approx 10R, so the circuit R is nearer 60R, giving 14.7kHz. Of course, there are now 2 cascaded rolloffs, so the actual -3dB point is shifted to a lower frequency by this. Not much good having a low corner frequency above our needed frequency. With the 470R pad input, the two series caps actually see 100R so the corner frequency is improved, but the match to the filter isn't. It's either a 50R path, or the effect of the mismatch must be very carefully considered. The load will reflect back through the diplexer and present the wrong load to the 2nd mixer, at exactly the 15kHz 2nd IF with which we are concerned. I believe that the 'right thing' is to keep the path to 50R as near as is possible.

The answer is to make the pad 50R in & out again, as it was originally, and increase all 3 caps to 2u2 (or preferably bigger). Although small footprint capacitors of this value will definitely have Hi-K dielectric (X7R or, even worse, Y5V), the non-linearity and capacitance variability will become far less significant overall since most of the signal now appears more equally on both plates of the capacitor. The signal level will rise as a result of this lowered capacitive impedance, so the increased attenuation of the 'original' PI-pad will be somewhat compensated; if more signal is needed there are other ways:
Either of these will restore the previous levels.

The increased value coupling capacitors themselves increase signal levels, so it might even be necessary to increase rather than reduce the pad attenuation. Comparing losses at 15kHz in the original circuit (with small capacitors and 470R arm in pad) with the revised circuit with 82R-100R-82R pad, we get:

attenuation at 15kHz from 50R source
Original circuit with all the original values, PI pad is 470-100-82R
With final mods except that PI pad is 12dB, 82-100-82R rather than any final value
With final mods except that PI pad is 9dB, 120-51-120R rather than any final value 16.6dB

So the gains in level due to the capacitors compensate for the loss due to the pad, all bar 0.9dB. The proposed reduced pad attenuation would give 4dB more signal than before and is not required.

Why not have more signal?

The CODEC has a finite dynamic range. We must ensure that our normal range of signals does not overload it. The input level is fine-adjusted during IF setup to get an appropriate level by altering RV604.
In the existing Picastar design, the DSP section uses an AC97 spec CODEC with an input range of "1Vrms (typical)". It does have an internal programmable gain pre-amp, but I don't know if this is used.
There is already a 2:1 resistive attenuator on each of the stero input channels right at the ADC input, using a fixed pot-down with two resistors each of 4k7 (it is actually a little more because of the nominal input resistance of the CODEC). In addition to this consideration, although we can use RV604 to wind down the wick, any more than a small reduction using RV604 implies that the signal out of the common-base stage TR603 is too high. This will give rise to more distortion and intermodulation products, and the gain-reduction is the principal reason for the pad in the first place.
Therefore it is good from every point of view to have no more overall gain in the circuit than we need, reducing the signal at the input rather than at the output.

Arguably it would be better to reduce gain in the earliest stage possible, but the pad is where it is and we can't change that physical arrangement on existing PCBs. Also, if we reduced gain in the 1st IF, the transmit path would also be affected, whereas at present it is not.
Reducing the gain of the common-base stage (from nominally 155V/V) could be useful, but the change in D.C. conditions would need careful consideration. Note that when fed from a 50R source the overall gain is naturally less and will be about 60V/V relative to the open-circuit source voltage due to the potential division of the impedances.
In addition to this, the pad usefully buffers the emitter impedance of the grounded-base stage, presenting a proper 50R load to the diplexer/filter.
We should therefore keep the pad to the very original values, 82-100-82R and trust that the resulting 0.9dB less signal still leaves things adjustable by RV604. I think it will. If not then you can increase the resistor RZ3, at the output of the PI-pad, which will have negligible effect on any important matching (do the sums and you will see).

Note that the potentiometer RV604 should not be set to zero resistance, since this will present a capacitive load of 1nF from C692 to the output of the buffer IC606B and create a feedback phase shift against the intrinsic output resistance of the op-amp that will promote instability in the op-amp. Back the pot off a little (a tiny fraction of a turn away from the end-stop) in order to avoid this - it will not affect the amplitude noticeably.
At maximum pot resistance there is a rolloff against the 1nF C692, but because the CODEC divider input resistance is 9.4k (this appears in parallel with the 22k pot) this corner is at 24kHz. This is rather low, but in any case it is better if the pot can be at low resistance to correspond with a smaller signal from IC606B and hence less distortion in TR603.

Most users following the calibration procedure will set the pot RV604 to somewhere close to minimum resistance - in 6 out of 6 Picastars where I am aware of the setting, this is the case. This is also good from the perspective of avoiding possibility of overload in the preceding stages due to reducing the level right at the output.

A problem that may be encountered if the pot resistance is set high is that the earlier stages will overload and clip before the ADC in the CODEC produces a full-scale output. The voltage follower IC606B will clip at around 1V from the rails (0V and +10V), but the common-base stage clips negative peaks on the collector at around +2.3V since the transistor 'bottoms'. This limits the stage as a whole to a maximum undistorted output level of from around 2.4V to 8.0V, which is 5.6Vpp. or 1.98Vrms. This (2Vrms) is the nominal maximum signal that can be applied to the "CODEC section" input at R103 and will produce digital 'full scale' from the CODEC ADC if the CODEC gain block is set to 0dB. Any reduction in CODEC input sensitivity due to RV604 being away from 0R will result in -ve peak clipping before this level is reached at the CODEC. Whether this is a problem or not depends on how the DSP code sets the CODEC gain block, but clipping before reaching nominal full-scale input is not advantageous. For example, if RV604 is set to maximum resistance (22k) then a nominal output from IC606B of 6.7Vrms (19Vpp) would be needed in order to achieve 1Vrms at the CODEC input pin. This is dramatically more than the 2Vrms that can be achieved (it is more even than the 10V power supply could provide) and may be a problem at high signal levels. The DSP code cleverly has internal AGC, which might use the CODEC gain block to vary the sensitivity, in which case a CODEC input level of 1Vrms may never be needed, but beware setting RV604 far away from minimum resistance. In all of six Picastars of which I know the setting of RV604 resulting from running the calibration, the pot is near minimum resistance, so there is not a problem from the previous stages overloading in any case.
The DSP code calls a CODEC-gain setting routine at Rx_block2, so clearly the gain element of the CODEC is used, but I do not understand the DSP code well enough to know whether this precludes the overloading mechanism described above. If it does, I have no doubt that the usual castigation will be forthcoming.

The noise-based calibration setting of RV604 sets the overall gain seen by the CODEC to a correct value, but has no knowledge of whether clipping will then occur at high signal levels due to the above mechanism. Too much gain prior to the gain-adjuster, requiring a high resistance setting of RV604 during calibration, would not be a good thing.

PI-pad again

You may wish to calculate different values for the PI pad in order to shift the pot setting a bit. For a small gain increase, to move the pot setting, I will re-iterate the suggestion to increase the emitter-end 82R of the PI pad.

OK, here are the sums. If we remove RX3 entirely, the PI pad input R is 82//(100+Re) = 82//132 = 50.58R. Still 50R! Work out the increased gain yourself!

In many of my simulations I have different values for the PI-pad resistors, for different attenuation. I apologise for any confusion this might cause, but it is a fundamental part of the design investigation process. Except for the original circuit, the pad is always 50R in and out, so the different attenuation will increase or decrease output by the corresponding amount. The final value of 82-100-82 is quite appropriate; in some cases even more attenuation may be considered advantageous. I might one day tidy the values presented here in order to avoid showing my intermediate calculations, if anyone asks for this.

The second problem:

The LF arm of the diplexer does not work as it seems!

The graph (below) is a simulation of the original ComboSTAR circuit from input to output, including the pad and common-base amplifier
The shape of the output vs frequency is immediately apparent: Is this a response you would welcome? The rolloff below 20kHz is caused by the too-small original coupling capacitors.
Response of original circuit!

The circuit for simulation is below:
Original simulation circuit

The Diplexer

The HF arm of the diplexer is not what it seems!

Original circuit showung diplexer

Although there is a proper-looking HF arm (C638 and R601, 10nF and 47R in series), it never has an effect.
In reality, at high frequencies, the resonance cap C639 (10nF) in parallel with the 330uH inductor, acts in series with the output capacitor C651 (100nF), presenting a capacitive load of 10n in series with 100n, shunting the input to the diplexer, and completely shorting the HF arm! The net capacitance is 9nF, which has a Zc of 1.65R at the 10.7MHz IF. This is a horrible mis-termination for the 2nd mixer, obviously not at all what was intended (or there would be no HF arm, C638 & R601). You can plainly see the antics of the filter Zin reflected in the signal at the input (green plot) shown in the response curve above. Spot the 50R if you can - it just happens to be about 50R as it meanders around 15kHz and 33kHz...

So either the C639 'resonance capacitor' must go, or we must seek some other way of removing the effect.
Why is it there?
It is present to make a simple Cauer elliptic filter stage, considerably increasing the initial rolloff slope.
A very precise and steep slope is often beneficial in DSP-based equipment, since the signal frequency and sampling frequency, both on transmit & receive, are 15kHz and 48kHz respectively - the first image frequency (on transmit) is at 33kHz and we would like to attenuate it considerably ("reconstruction"). A filter of this style can give a deep rejection notch at this frequency (but the notch of this one 'misses').
On receive, there is often a problem of aliasing. Any signal (in practice it will be almost entirely noise) at 33kHz or the higher-order alias frequencies (there is one at 30kHz) can be sampled back to 15kHz or so, and be impossible to distinguish from a genuine signal in DSP. If it is mainly noise (at high IF gain) then it will raise the noise floor and lose overall sensitivity; not what we would choose.
If the 33kHz & above stuff is reduced by at least 10dB by the filter, and if it is noise, then it will have negligible effect on the resulting noise level to the DSP. So we would need an anti-aliasing low-pass filter that has a corner frequency, safely above 15kHz and attenuation of, say, 6dB at 33kHz.

In the specification for the CODEC used on the DSP block (AD1885), it is clear that the CODEC itself has excellent attenuation to aliasing frequencies, so the filter in the diplexer need not provide further filtering, although it could still be useful to prevent alias-able signals from reaching the amplifiers. This CODEC is now obsolescent, although surplus parts are still obtainable. The DSP processor is obsolete. It is possible that someday the entire DSP section (CODEC, DSP Processor and peripherals) will be entirely redesigned, although this is unlikely, since it could be a huge effort to port the software to a different architecture. Any future replacement may use a 'straight' CODEC that doesn't include this filtering, although it is unlikely. So it seems reasonable that we aim to design a diplexer/filter that will have rejection of the alias frequency. Even if this is not essential with the AD1885 CODEC, it can certainly do no harm whatsoever. If this target fails to realise a filter, then the criteria can be altered.

The original filter has negligible relative attenuation at 33kHz... Well, maybe 1 or 2dB, so does not significantly attenuate the alias frequency. This, in itself, may not matter so much when the CODEC itself has excellent rejection, but it seems at face value that the filter topology was originally expected to provide such attenuation (otherwise why does it incorporate a deliberate rejection notch).

The markers at approximately 15kHz (wanted 2nd IF) and 33kHz (quantisation aliasing frequency) show how little rolloff the original circuit has. Maybe the deep notch around 90kHz was intended to be at the alias frequency?
Original response again

On transmit, there is an odd situation: the 15kHz drive from the original buffer amplifier is at low impedance (emitters of TR604 and TR606, reduced to near zero by 100% -ve feedback in the stage), not 50R, so the filter will not necessarily work as expected. It would be good to maintain 50R at this point, and indeed most filter design aids assume that there is a defined non-zero source impedance, but of course a source-match would lose us half the signal, which might be a problem. Once again, the d.c. block C632 is only 220n, see above! This should probably be increased also to at least 2u2, as for the Rx path, in order to avoid the rolloff starting right at the 2nd IF.

If the reconstruction action of the filtering on Transmit were below par, some image components could be passed into the modulator and will cause 'off-frequency' signals at the 1st IF. These will be at least 15kHz above the desired IF component, and will be greatly rejected by the crystal roofing filter. My ITT 10.7MHz filter has attenuation of greater than 85dB (typ 100dB) when offset by 15kHz, so even if any image energy is present, it will be sliced away! Wonderful! Nevertheless, our filter should be as good as we can reasonably make it, even if only to show willing! The AC97 specification tells us that the DAC has image rejection, so further filtering is not essential. Nevertheless, if the diplexer/filter is being considered, it would seem incongruous to design for a cutoff at some other frequency unless it proves necessary in order to realise a filter.

I decided to continue first with the receive path, since it is switched separately from transmit. On achieving a reasonable receive filter implementation, it will be appropriate to study the transmit implications.

On receive, we would like to keep a good rolloff rate (slope) if possible, but the main criterion is to avoid the dramatic error in termination of the 2nd mixer. Since a redesign of the diplexer is required anyway, we need some criterion for the parameters so may as well choose to reduce any possible alias frequencies.

We could get an easy extra pole on the receive path; by fitting a suitable capacitor across the common-base amp collector load. This will not affect any other elements because of the isolating effect of the grounded-base stage and of the subsequent voltage follower. We need a value that will allow 15kHz 'unattenuated' but will rolloff the 33kHz alias. The resistor R620 is 5k6, so we could choose 1nF with a -3dB freq of 28.4kHz, or 1n5 which gives 19kHz - rather close, since there will be attenuation below the -3dB point! So I think we should choose a 1nF value, placed across R620 which is physically easy to do but will couple in rail noise. It might be possible to connect to the ground-plane rather than the rail, theoretically better but not so easy to do. We may need to consider tolerancing, since the wanted and unwanted frequencies are rather close together.

However, this extra pole is not needed, so long as the CODEC has deep rejection of whatever alias-able stuff comes through (it is only noise, as mentioned earlier).

Sanitise the Filter - even more changes!

Now we must sanitise the filter/diplexer in order properly to terminate the 2nd mixer. This is what was intended in the original design, but was not achieved.
Cauer is out, unless we perform trickery, or we get back to square one with the incorrect HF mixer termination. I considered placing 47R in series with the resonance cap C639 (10nF), which then reasonably terminates the HF signal component if the original HF arm is removed. This, however, reduces Q and makes the filter considerably less effective, but it may still be an option. I am not convinced that it actually much better than a straightforward filter, given the closeness of the two frequencies, so will discount it for now.

The task now is to see what sort of diplexer we can reasonably achieve without hacking the PCB. If there is no reasonable solution to propose without major PCB surgery, it is probably better to keep quiet!

What we should do

Clearly our options are limited with the existing physical layout, but it seems reasonable to remove the 10nF 'Cauer' cap C639 and increase the inductor to 680nH. In addition, all the coupling capacitors in the Rx path at least, should be increased to >2.2uF or preferably 10uF. The response if this is done is certainly better by far than the original. A filter of more elements would be highly desirable. As a design exercise, we must choose a cutoff frequency and slope for the filter. There is no reason why we should not try to attain the requirement for it to cut-off the alias; indeed, when considering the Transmit direction this is also a useful aim.

The original filter at 33kHz is maybe 1dB down on 15kHz, being generous! It peaks at about 22kHz and rolls off either side.

Here is the response and schematic of the filter modified as described to an 'L' topology, but with no change to the 10nF in the HF arm. It has a clean rolloff, and the mixer is properly terminated at the required frequencies. It has rejection of alias frequencies, so there may be no need to modify our tentative target requirement.

The recommended filter's response

In the schematic below, I have shown the PI-pad values that I used; the graph above uses the standard values which give 3dB more attenuation.
This is a part-way solution and is not final.

final circuit

So What About A Cauer Filter?

I mentioned earlier that it may be possible to use a Cauer filter, with it's resonant series section giving an extra rolloff, as in the original. Indeed, if the high frequency terminating arm is made up from adding a 47R in series with the capacitor C639 (C2 in my simulation circuit above), and the existing HF arm removed, the termination is OK at the high frequencies and the Q of the resonance stays just about high enough to achieve a perceptible dip (but not a sharp dip as with the original).
My feeling is that, since the 'regular' filter gives a good response, that there is not a lot of point changing to a Cauer, with it's worse phase response and group delay. However, for those who feel that I would be slacking if I didn't at least cover it with analysis, here it is:
Cauer-2, optimisedcuaer-1 optimiswd

cauer-2 schematicCauer-1 schematic

Note that I have changed the coupling capacitors from the original (too small) values here, since this is required anyway. Although the scales for the responses have altered, it can be seen that distributing the 50R HF load between the 2 arms of the filter (R10, R11 above) results in a deeper trough due to the higher Q of the resonant series arm. These two configurations are the best I could manage with this topology. Note that the change to a high value of R1 (47k) in the above schematics is disabling the original HF arm of the diplexer. The HF termination is done with the new 47R (R10) or with the series combination (R10, R11).

The attenuation at 33kHz relative to 15kHz is approximately:

So I conclude that the Cauer, once sanitized not to shunt the output capacitively at higher frequencies, does not provide any great benefit over the simpler, conventional 'L' filter.

In any event, we must make the identical circuit serve in the Transmit direction also.

Final Filter

After studying the Transmit Path, it seemed a good idea to use a 'T' low-pass filter rather than an 'L' configuration, mainly in order to avoid a capacitive load on the transmit-side buffer. The 'modified Cauer' (Cauer-2) above almost gets there, by presenting a 22R resistive load at high frequencies, but there are other possibilities.

When studying across sheets of the schematics and drawing a scrap circuit of things, it became obvious that the output of the MixAdaptor section is biassed at 2.5V, so the diplexer receives this d.c. offset together with the signal. Then, following the filter, there is a capacitor to 'isolate' this d.c. component, followed immediately by reinstating it in order to bias the switch IC604. The implication is that there is no voltage across C632, so I measured it: 12mV! There is no need for C632, let alone a 10uF-value C632; it can be replaced with a short-circuit (and the bias divider R625, R626 removed or not fitted if desired).

With this in mind, I considered replacing C632 with an inductor rather than a short-circuit, thereby building a 'T' low-pass filter consisting of RFC612, C651 and the 'C632' inductor. This would allow not only the emitters of TR604, TR606 to see a load that increases at high frequency, but also gives the filter another element. However, on looking for inductors of 'reasonable' value, hundreds of uH, in a surface-mount package small enough to fit in place of C632, it became apparent that they don't come this physically small. One thing we are avoiding is hacking the PCB...

Undeterred and raring to see if it was worth trying, I attempted to design a 'T' filter that would have something like 50R looking both ways in and out of it, a symmetrical filter, but with the bias towards the receive direction being good, since on Rx we are trying to pick signals out of received -um- stuff. On Tx the signal from the DSP is as good as it can be. After a good bit of head-scratching and nearly wearing out Elsie <g>, I tried some 'handy' values and hit gold! By using a larger value for C651, 200nF (it was 100nF for the 'L' filter) and adding 330uH in place of C631, I ended up with a filter in the receive direction with a sharper cutoff than before, and one in the transmit direction with a reasonably respectable behaviour! Too good to ignore, I discovered that the axial 330uH chokes from Farnell would fit the surface mount footprint if the legs are bent appropriately! The body stands vertically, but who cares? It's a bit tight for space, because of adjacent components, but it fits (note that Glenn later used a different way of mounting it that may be more appropriate).

I'm sure that there are other implementations that will suffice, but at least this one meets with my personal aim of presenting inductors to the mixer and Tx buffer, and it also allows a diplexer to be constructed that properly terminates the 2nd mixer.
Henning DK5LV has used different component values in his implementation; you can choose. Henning has also used Wima MKS capacitors in order to avoid the poor behaviour of Hi-K ceramic capacitors; I have chosen to use 'non-Hi-K' NP0 ceramic capacitors instead.

I fitted two 100nF 1206-body 5% NP0 capacitors in parallel, one above the other, for C651; these are expensive at 90p each (Farnell 882-0210) but that is not a major problem in the scheme of things. They have a minimum order quantity of 10, so fitting two is also no problem! You could maybe use X7R dielectric at a pinch for cheapness, but see my note elsewhere on Farnell offerings. It is not worth putting anything worse than NP0 in any filter or tuned circuit.

The inductor fitted nicely, albeit a bit tricky to position in the space available.
In all of this, I have ignored group delay (as I believe did the original design). Since we only use a small part of the full bandwith it is likely but not certain that the effect of group delay will not be significant; please contact me if you would like to comment on this (or anything else).

'T' lowpass schematic

This shows the cutoff of the whole receive path from diplexer input to common-base stage output. This simulation includes the 'extra' pole at the collector of the common-base stage (C8 above), which is not really needed.'T' filter plot in receive direction

Below is a magnified view of the above transmission plot for the complete circuit. The span 15kHz±3kHz has amplitude variation of about 2dB. For SSB we need 3kHz overall bandwidth (±1.5kHz), which is flat to about 1dB.
Close-in filter response

Well, that filter looks pretty good. Please note that this is with reduced attenuation in the PI-pad (120-51-120R). I found that the original 82-100-82R, with 4dB more attenuation, gave adequate signal with the output pot near minimum, better for achieving low distortion and intermodulation by running at lower level in the amplifiers.

The extra pole on Receive due to the capacitor across R620 (5k6) is further 'improving' the slope, but the 'T' LPF is alone is amazingly effective. The increase to 100nF from 10nF of C638 has maintained a 50R load except for the onset of the amplitude rolloff, as can be seen by the slight 'kick' upwards of the input amplitude trace (in green above) at just over 20kHz. This is difficult to avoid without considerable extra poles or by changing the original design criteria (possibly relying entirely on the CODEC filters) and is not a problem.

I think that this is getting close to the best we can achieve without adding a daughter board. Although it would obviously be inviting to have a fresh start with the Rx-side 2nd IF, the performance of this 'low intrusion' diplexer/filter is more than adequate to ensure correct termination and to provide some alias rejection.

The above schematic represents my modification to the design. I have been persuaded that it would be a Good Idea to increase C638 (C1 on the simulation) from 10nF to 100nF in order to minimise the 'gap' before the HF arm 'comes in'. This will reduce the high termination impedance (visible on the simulation plot as an input amplitude increase) that otherwise occurs between 30kHz and 300kHz. For the sake of one more change we may as well get it right. This is shown on the simulation above. It is best to use another of the NP0 capacitors.

A better input impedance over the full frequency range is obtained with C638 at 200nF, but because the input becomes shunted by the HF arm at 15kHz, the gain and slope of the transmission characteristic are adversely affected also. Stick with 100nF!

Coupling Capacitor types

As we all know, Hi-K ceramic capacitors have poor initial tolerance, temperature coefficient of capacitance, voltage coefficient of capacitance, and have high losses dependent on frequency. The X7R and Y5V should not be used in tuned circuits of any sort. Preferred typed for tuned circuits are NP0 ceramics or, if their self-inductance is acceptable, plastic capacitors such as polystyrene, polyester or polycarbonate.

When used as decoupling capacitors, the characteristics of Hi-K ceramics are usually tolerable (sometimes paralleled with a smaller value capacitor better to handle high frequencies), but are they suitable for coupling signals (d.c. blocking)?

Consider the normal requirement for a coupling capacitor: it must pass the entire a.c. signal but block the d.c. level. If it actually does this, then the a.c. signal across it is zero and dielectric type not of major significance. If it has a significant a.c. signal appearing across it, then the dielectric characteristics determine whether that signal will be affected. Perhaps the most worrying of these effects would be voltage non-linearity of capacitance, where the capacitance and hence voltage drop would depend on the instantaneous voltage present across it. This would be manifest as non-linearity of signal drop with instantaneous amplitude, a source of distortion, which we clearly do not want!
Since this depends on the voltage across the capacitor, it is clear that (for a given frequency and circuit impedance) a larger capacitor value will produce a smaller effect overall than a smaller one, since it develops less voltage drop and therefore has less overall effect.

If our Hi-K capacitor has a value small enough to allow a significant a.c. voltage to appear across it, signal distortion is likely. However, if we use a Hi-K capacitor of sufficient value that any variations of voltage-drop due to the dielectric are insignificant compared with the full signal voltage, then not only is the Hi-K effect far less important, but also as much signal level as possible will be passed to the subsequent circuit.

The original Picastar uses several 220nF Hi-K coupling capacitors in nominal 50R paths in the 2nd IF stage, which operates at 15kHz +- 3kHz. At 15kHz, 220nF has an impedance of 48.23 Ohms. This is the same as the circuit impedance, so half the signal will be developed across the capacitor, giving not only signal attenuation but also the likelihood of distortion due to the dielectric behaviour. This is not good!

I have suggested using 10uF, or at a pinch 2u2. At 15kHz, 10uF has an impedance of 1.06 Ohms, which is as near zero as we might like. This means that not only will it hardly attenuate the signal in the 50R path, but also that any capacitance variation will have only a very small effect on the signal - it will not give significant distortion.
Clearly, even larger values would be better, but 10uF is a useful value and is obtainable in small SMT sizes that will fit the pads. Although, in most cases, the actual terminal voltage difference is small, it is wise to choose capacitors with 10V rating (this is the supply voltage) for safety. X7R is the best choice of dielectric, but Y5V might still not be that bad.
Farnell offers X7R 10uF 16V 1206 10% capacitors (1463368) for 47p each (singly). The higher voltage rating of these should provide an excellent margin. A 10V part is also available (1288264) for 19p each, but these are priced in tens. Either of these would be a good choice.

If it were physically possible, we could use plastic dielectric capacitors (polystyrene, polyester, polycarbonate) or mica (at a cost). But values of 10uF are not really practical; we need a large value in order to avoid the rolloff. Maybe you could consider using these, but bear in mind that we are trying to improve things, not achieve perfection. The capacitors mentioned in the previous paragraph will fit the existing PCB pads and, I believe, are a colossal improvement.


Actual response measurements for the suggested filter have been performed by others and show good conformance to the theoretical shape.

Henning DK5LV

Henning has built his diplexer/filter with his own chosen values. He says "I have changed the diplexer after the second mixer to a Tshebychef LP 0.05 dB ripple giving 20 dB return loss in the passband (two times 330 uh, 177 nF (150 nF + 22 nF in parallel; type Wima MKS) to ground in the middle".
These values give about 0.25dB less gain difference across 15kHz +- 1.2kHz, but considerably less attenuation (about 6dB less) at the image frequency. Because the image and wanted frequencies are only an octave apart, it is a difficult compromise, but I am happy with the values I used. Henning has wisely considered my change philosphy and chosen his own filter preference.
You may prefer to use Henning's values, but remember to use NP0 or MKS capacitors for stability and low distortion.

Dave G3SUL

On the topic of anti-aliasing, Dave G3SUL has kindly pointed out (message #4345 on the picastar-users group) that the AC97 specification requires that compatible CODECs "have on-chip filtering incorporated which gives rejection of at least 74 dB at the Rx aliasing frequencies, and Tx anti-alias rejection of 40 dB for all output noise from 28.8kHz to 100kHz." Dave suggests that therefore "any additional anti-aliassing rejection provided by modifications to the 15 kHz LPF and buffer stage is of no practical consequence to the anti-aliassing performance."

Even though the modifications might not provide any eventual improvement to the anti-aliasing performance, it is important to bear in mind that the reasons for changing the filter are:

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