Bus Switches as Analogue Switches


These points, plus detailed figures and derivations, are presented below, together with my recommended 'cure' based on interpolating the device parameters given in the manufacturers' data sheets.

In the fullness of time, you may find a Step By Step Guide to modifying your PICASTAR on this page, or at least a list of 'chain-bottom' resistor references for Glenn's ComboBoard and what value to shunt them with to obtain correct biassing for low on-resistance and best dynamic range. They all need changing. But see my disclaimer.

As a late note, the first manifestation of improper biassing has surfaced in the 2nd IF Transmit Buffer, where positive peak clipping occurs in the Bus Switch IC604. Similar effects might occur throughout the PICASTAR, since all the bus switches are biassed incorrectly at mid-rail.


If you decide to use any of the information here, you will make your PICASTAR non-standard. Even if you wish to do the changes on a 'new-build' STAR, please build it first using all the standard build information, with no changes from the published design. Also you need to calibrate it using all the excellent BASIC programmes, to verify that it works correctly, before you modify it. This is what I did myself.
If you do not 'RTFM' (read and use all the PICASTAR documentation in the Yahoo! Groups Pic-a-Project group before you modify your build in any way, then no-one will be able to help you to get your own build working. You must join this group in order to obtain (and be permitted to use) the design information that you need. If you then need help (with an un-modified STAR) you will get it by posting your problem on the picastar-users group. If your STAR is modified in any way, then the very helpful people on the picastar-users group will probably not be able to help you.


This is very much a Work In Progress and will be changed and added to in a wholly personal way. If you are viewing this it is either because you have stumbled upon it or have been invited to see it. Please do not share it with others; when the time is  right I will do that myself.
I will happily receive comments or criticisms in the usual way.

The work below arose from my study of the usage of bus switches in PICASTAR (© Peter, G3XJP) but is not limited to that use.

PICASTAR (STAR) uses many Fairchild FST3125 and FST3126 devices for all kinds of routing and switching purposes. These are sold as Bus Switches, intended to be used for interconnecting or isolating logic buses. By their nature they are bidirectional, and they have excellent performance in the intended application.

Texas Instruments also has 'equivalents', the SN74CBT3125 and SN74CBT3126. Do not use 'C' suffix parts, which have 'undershoot protection' circuitry that adds to the 'off' switch feedthrough capacitance.
Also there are some 3V parts from TI, which you should avoid since they have built-in voltage generating oscillators to give adequate enhancement voltage - not a good idea in the same device that is switching nV radio frequencies.
The TI parts look similar and I intend to check them later.

There are probably other manufacturers of similar parts, please let me know what you are using.

STAR uses the devices in a switching mode in the first & second mixers. They are rapidly switched on or off at local-oscillator speed and modulate the input waveform, acting as cheap and excellent mixers.

The devices are also used as general route-steering switches, mainly in 50R paths, for enabling and disabling specific signal paths. An example is the use in the Bandpass Filter area, for switching into circuit the desired filter and isolating the others.
In all such uses, the switch pins are a.c. coupled and one side is biassed by a potential divider to be at half the 5V supply rail. This has been said to provide the maximum dynamic range. But it doesn't. Read on...

Study the datasheets

If we look at the Fairchild information, we find that the single N-channel MOSFET used for the switching element has a gate threshold of about 1V (Fairchild AN-5007 "An Introduction to Fairchild Switch Products"). Provided that either the source or drain is at less than this threshold (the FET is symmetrical), the FET is enhanced and a conduction path exists between source and drain. If the gate voltage is below this threshold, the channel is off and isolation between source and drain results.

However, as the source/drain voltage approaches the gate threshold, the channel resistance increases, as is normal for a single FET. It does not suddenly change from very low to very high.  Fairchild indicates that the point at which the FET is 'off' is with a Vgs of 1V, but at levels approaching this, the channel will have high resistance.

We are given a feel for this by the specification for the FST3125 and FST3126 devices, which are idential except that one has an inverting logic buffer on the gate and the other a non-inverting logic buffer. In both cases, this buffer ensures that the main pass FET gate voltage is either at one of the device supply voltages or the other, disallowing intermediate gate voltages.

If the FET gate is at 0V, then the FET is 'off' and will remain off so long as neither switch port is taken below -1V.
If the FET gate is at Vdd (probably +5V), then the FET will be 'on' for as long as either of the switch ports is below Vgs, i.e. less than about +4V for this supply voltage.
But as the switch ports vary in voltage between 0V and Vgs, the on-resistance of the channel will vary, being least at 0V and most at the Vgs threshold, where it can be considered to switch off. The actual resistance value is a function of the design of the FET.
Switch on-resistance
For many signal-gating devices, such as CMOS bilateral switches, the manufacturer shows how the switch on-resistance varies according to the voltage being switched. With CMOS switches the highest resistance occurs at nominally mid-rail, when neither the P- nor N-channel element is fully enhanced; either side of this the resistance decreases as one or the other FET takes control.
But for our Bus Switch, there is only an N-channel device, so the on-resistance increases continuously as the switch voltage increases, until eventually the switch turns itself off. This is not at all a problem in the anticipated digital use of the device, but when used as an analogue switch it is very important indeed.  If our switch ports are at 0V then the FET is fully controlled by the logic input, but as the ports approach the threshold voltage Vgs so the resistance increases, affecting the switched circuit.
Varying the supply voltage
Some designers who wish to use Bus Switches as analogue switches have employed higher than usual supply voltage on the device, to maintain a high threshold point and increase the range of low on-resistance, often up to the manufacterer's 'Absolute Maximum' rating of 7.0V.
This, it is pointed out by Fairchild, should not be done. They say:
" Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the  recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only."
In other words, the absolute maximum is not intended to be a normal operating condition, but the limit of a safety zone.
Proper operating levels
Fairchild, like other manufacturers of ICs, does provide a statement of the conditions under which their devices may safely be operated; the "Recommended Operating Conditions". For the FST3125/FST3126 this states:
"The Recommended Operating Conditions table defines the  conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings."

The maximum recommended Operating Power Supply is 5.5V.

Interpret the data for our usage

The Fairchild data gives us in insight into how the FET on-resistance varies with channel voltage.
The 'Switch On Resistance' at 0V with a Vcc supply of 4.5V is typically 4R, maximum of 7R .
The 'Switch On Resistance' at 2.4V with a supply of 4.5V is typically 8R, maximum of 15R.
The 'Switch On Resistance' at 2.4V with a supply of 4.0V is typically 11R, maximum 20R.
From this we can see the enhanced channel resistance.

These figures really relate to how the Fairchild FET channel resistance varies with the enhancement voltage:
Vgs = Vcc - Vin/out
Ron (Typical) Ohms
4 Ohms
8 Ohms
11 Ohms
Ron (Maximum) Ohms
7 Ohms
15 Ohms
20 Ohms

The transfer characteristic can be likened to most NMOS FETs, and will show a similar shape. If we plot the values above and fit a curve to them, it looks like this, using Average values. It's a shame we don't have more points:
Bus Switch FET characteristic

This shows clearly the way that the FET will be fully off by the time the Vgs is 1V, as stated by National.

In most PICASTAR usage, the switch is used in a 50-Ohm circuit, so if the on-resistance is significant compared with 50R then it will neither be efficient nor will it permit a reasonable match to be maintained.   In the Bandpass Filter section, there are two switches used per signal path, one at each end of each band's filter, but two of the FETs in a package are paralleled for each switch, so it is better than at first sight (the other 2 FETS serve other purposes).
That's Fairchild; what about TI?
These figures can be compared with the TI part SN74CBT3126; typical values are  used:
Maker F TI
Vgs = Vcc - Vin/out 4.5V 4.5V
2.1V 2.1V
1.6V 1.6V
Ron (Typical) Ohms 4 Ohms
5 Ohms
8 Ohms
10 Ohms
11 Ohms
16 Ohms
From this table it is clear that TI devices have higher on-resistance. Since they also are specified to have higher 'off' capacitance, they do not represent a good choice and TI parts are best avoided.

This data makes more sense to us if it is transposed to be the resistance against the actual applied voltage on the FET. I have only done this for a supply voltage of 5.0V, since this is a condition of the 'typical' values. If the supply is at the low limit of a 78L05 regulator, the X axis must be offset by -0.25V.

On-resistance vs switched voltage for TI & Fairchild switches
Although I didn't fit a curve, the trends are obvious. The graph shows clearly the superiority of the Fairchild device (from published 'typical' specification). It also gives us a feel for the operating voltage (bias) we might wish to use - it won't be anywhere near 3V or we have no dynamic range! 
Note that the value at 0V on the pin is probably virtually the same as at 0.5V; using the data-sheet figures this value does not appear.

Best Operating Condition

To obtain a low 'on' resistance for the switch, we need the lowest possible 'bias', or steady-state voltage that we can tolerate whilst still allowing a reasonable symmetry of signal swing on either side.
Clearly, from the graph above, voltages above 3.5V are no use at all, since the FET is switching 'off' when we need it 'on'. To get a reasonably symmetrical characteristic, we might choose the bias point to be, say 1.5V, although even this would result in a large signal resistance variation for large signals. This would modulate the path resistance and is undesirable since it represents voltage-dependent non-linearity.

Let us consider the normal habit within PICASTAR.

In all cases that I recall, where signals are switched using Bus Switches, the source or drain is biassed to half the supply voltage of 5.0V. This is done in the hope that it provides the maximum voltage swing.
This would be the case for a CMOS switch which has minimum on-resistance for inputs at each supply rail due to the paralleled PMOS and NMOS switches, but these bus switches have only the NMOS element as explained before. As can be seen from the graph of typical characteristics above, the switch resistance is low for an input of 0V (around 4 Ohms) but rises considerably as the switched signal increases in voltage until, at an input voltage of 2.75V, the channel resistance is 10 Ohms, rising rapidly thereafter as the FET turns off, which is not very useful for passing signals in a 50-Ohm circuit.
Remember that the action of 'turning off' is not due to the switch control input pin, but is entirely due to the voltage level actually being switched by the nominally 'ON' switch.

What about Worst Case figures?

Bear in mind that we are still dealing with typical figures; as designers we should take note of worst-case figures. This gives a different result:
Worst case FET
The Typical plot uses the same data as before, for comparison. Both sets are derived from the Fairchild data-sheet figures. It is easy to see that the worst-case figures are, indeed, a lot worse than typical figures! If we look closely, there is a footnote on the data-sheet that further qualifies the typical figures, saying "Note 4: Typical values are at VCC = 5.0V and TA = +25°C.
This means that the 'typical' figures don't actually apply if our supply voltage is not the 'nominal' regulator output of 5.0V, nor at temperatures other than 25°C.

Which figures should we use?

In a commercial design environment, for this type of device, we must consider the worst case, whether we like it or not, unless it is clearly demonstrated and recorded in the design specification that the conditions of use are limited to those of the typical figures.
If we only use the typical figures, our production department could end up manufacturing items which do not work properly in hot or cold conditions, or if the supply voltage is less than 5.0V, although the chip manufacturer says his devices are within specification; they are.  Who will tell The Boss that the day's manufacturing is all faulty, that Fairchild won't accept any liability, nor will they take back the unused chips?
We also have to tell The Boss that, in future, we must purchase specially tested chips from the vendor, all characterised to ensure that, in our usage, they have characteristics that are no worse than typical!
In the end, the chip manufacturer will select out all the 'better' chips for sale to our Company at premium prices, and everyone else will get the rest, still within specification, but all worse than the 'typical' figures.  This used to happen with resistors; all those close to the nominal were selected out and sold as 2% or 5%; if we bought 10% for cheapness and tried to select those within 2% we would find a gap in the value distribution - someone had been there first (this is not so prevalent with resistors these days).

So what does our design department do?  I have seen various schemes, some assuming that the worst case is the 3-sigma points of a normal distribution pattern (it isn't necessarily so) and some requiring a design point somewhere between typical and worst-case, but the only satisfactory way for our production designer is to assume that every device of one type can be at worst-case, or to seek a better device to use.
Apply statistics over the whole design, but not over single component types. If you conclude that 1% of production will statistically be rejected because of tolerance effects, so be it. Just be sure that this is what the boss is comfortable with. I have seen warehouses full of such rejects awaiting 'rectification' - even 0.01% of a million units a day is an awful lot!

After all we might say to justify using 'typical' values, the device manufacturer provides worst-case specifications so that we can use them collectively to calculate the limits of our design, not just for fun. If 'typical' figures were sufficient, his daunting worst-case figures would simply not be published. They are for our use and our protection against an unsound design.

Amateur use

For us, as amateurs, it is highly tempting to use the 'Typical' figures (and most amateur designers do just this), but what if one of our ICs is at worst case, as it may well be? When we build a PICASTAR, do we test each circuit block to ensure that the performance is what we would like? Do we then change each and every component that we deem to be faulty because it is outside its Typical specification? Do we even know which part is causing the problem?

We have to use the device, because it has been designed in and there may be no better alternative part. It may not even be apparent that there could be a problem. After all, you are probably not the original designer...

Operating bias point

Suppose I have an AC signal of 0.5Vpp to switch with a bus switch, in a 50R circuit. I believe that I can tolerate an on-resistance of no more than 5R for the switch, 10% of the circuit impedance. That sounds reasonable.
For a 0.5Vpp AC-coupled signal, the peaks are at  -0.25V and +0.25V. We need to bias the switch to meet our requirement for 5R on-resistance with minimal change for our signal, or we end up with signal distortion due to peak compession as the on-resistance rises.
Let's see how our worst-case bus switch fares:
We would like the bias point to be as far from 0V as reasonably possible, since at 0V we run into clipping (clipping probably won't occur in practice until a clamp diode conducts, however).
  1. The positive peak must not see a switch resistance significantly greater than the negative peak, or the circuit will be non-linear.
  2. At no time must the on-resistance exceed our target of 5R
  3. We must allow that our supply regulator is specified to provide 5.0V +- 0.25V, so the supply may be 4.75V
  4. There may be additional power voltage drop due to circuit resistance; let us provisionally allow 0.1V for this.
 To fulfill item 2, the worst-case device shown in the graph must have a lower on-resistance than it can achieve (it extrapolates to about 6R with the whole 5V as Vgs). We have failed and can either try different conditions or look for a more suitable device.
In our favour, the 'worst case' applies to the full temperature and supply-voltage range. It is the worst case. We are not expecting to operate our devices at extremes of temperature, but they may still be above the 25deg C at which 'typical' applies. But we have no figures available except 'typical' and 'worst case'... Should we guess at something?

Now let us consider a 'typical' device, using the above criteria to determine a bias point.

To fulfill item 2, on-resistance < 5R, our Vgs must be greater than 3.5V, which we can achieve by restricting the whole signal swing. With our (4.75V - 0.1V) supply voltage, to obtain a Vgs greater than 3.5V, no part of our switched signal must exceed (Vsupply - 3.5V), or our Vgs will be inadequate and on-resistance too high.
The signal must therefore not exceed +1.15V on the positive peak. We can achieve this for our 0.5Vpp signal by biassing the switch channel so that the peak remains below +1.15V. Our bias point must not exceed (1.15V - 0.25V), 0.9V to achieve this.

As a check, we do not want the -ve peak to clip either, so at our chosen bias point the -ve peak must not drop below 0V. It will be 0.25 below the bias point, so will not go below 0.65V, which is OK.

I have assumed that our signal is symmetrical in amplitude above and below the a.c. mean value. This is true for a sinewave, but is obviously not true for an asymmetrical signal, so we must be very careful with our conclusions. For a small duty-cycle signal, practically the whole peak-to-peak voltage may appear either above or below the mean value! But let us not worry about that yet.

We have fulfilled item 2 by setting the bias point at 0.9V, and could reduce this without clipping the negative peaks in the chip protection diode (if  it has one).

Let us check on item 1. We want an insignificant variation in resistance across the range of our input signal. If we are biassed at 0.9V, the resistance on the positive peak is 5R, because that was our criterion in item 2.
At the negative peak, the device pin will be 0.5V lower than on the positive peak (it is a 0.5Vpp signal). This will put (+1.15V - 0.5V) = 0.65V on the switch input. Our Vgs will be (Vsupply - 0.65V) = (4.65V - 0.65V) = 4.0V. From the (typical) graph, this Vgs gives a switch resistance of around 4.3R. Our switch has changed resistance from 5.0R on the positive peak to 4.3R on the negative peak. We must decide whether this is excessive. If so, we could try moving the bias point lower, since the on-resistance curve is non-linear and there is range to spare.

Best signal range method

If we wish to allow the largest possible signal to be applied to the switch without it either dropping below 0V or causing the switch resistance to exceed out 5R target, we clearly have a range span of the signal from 0V to the 5R on-resistance point at 1.15V (the figure we derived above).  to achive this, we will want our bias point to be in the centre of this range, +0.575V.  This will also fulfill the requirement for our 0.5Vpp signal, and since it is lower than the previous figure we would expect less on-resistance variation with signal. This is a good choice for bias point.

Real figures

The calculations above have used the manufacturer's specified figures for the device. Nothing is invented or guessed at, except our own particular criteria for on-resistance and signal amplitude.
We have seen that a worst-case device is no use to us at all unless, maybe, we can change our criteria for on-resistance. This is unlikely, given the extent of change we would need!
Also we have seen that, within our criteria, a bias point of 0.575V is appropriate.
If we could tolerate a maximum on-resistance higher than 5R, and didn't mind non-linearity of resistance, the bias point could vary upwards - maybe enough to allow a worst-case device to be used. The calculation is easy, but the acceptable criteria must be defined first.

Can we go -ve of ground?

Up to now we have steadfastly refused to allow our signal to go below 0V on the basis that it may 'touch' a protection diode, with disatrous consequences for signal integrity!  Normally, protection diodes are built into the substrate of a chip and are often unisolated parasitic diodes. Not always, though. Most of us have encountered the type of level converter that permits an input (or output) to rise beyond the +ve supply; they are not uncommon. There are also plenty of devices that have no diode clamp to the -ve supply.

If the bus switches fall into that category, it would enable us to take the signal negative without any conduction until the channel dropped far enough below the supply to cause conduction of a nominally 'off' FET.
This would happen because the NMOS FET gate clearly cannot be taken below the rail by the driver buffer; so when the source or drain becomes negative enough the FET will turn 'on' in spite of the control input selecting the 'off' condition.  This is not the conduction of a clamp diode, but the unwanted conduction through the FET - it turns itself on. This will happen by the time we reach the gate threshold, just as before. For our typical device, we have established that this is at around 1.3V. A silicon clamp diode would conduct at around 0.5 to 0.6V, of course.

Clamp Diodes

The Fairchild datasheet for FST3126 tells us that the Clamp Diode Voltage for Vcc of 4.5V is max -1.2V at Iin=-18mA. That current is quite large, so it may represent a very 'soft'  substrate diode, but the figure is actually very close to our expectation for the threshold of the FET.  We will have to use a meter to check it.
What do we find? There is a diode conduction path present. It seems to have lower than expected conduction voltage (0.5V; a 1N4148 has 0.6V) so it might be a FET substrate diode. We had best avoid significant negative excursions (down to -0.2V or -0.3V is probably acceptable).
We do not need to worry about spurious conduction through the 'off' FET, because clamp-diode conduction occurs first.

It is OK to let our signal become a scrap negative before we need worry about the clamp conducting. This is still a better bet than trying to operate at a positive level at which the FET on-resistance is too high!


Anyway, we started off by considering the best bias point for the Bus Switch and wondering if 50% of the 5V supply, as originally used, is a good level.  It is not, as we have seen.
The graph shows us that the TI device already has over 9 Ohms of on-resistance when biassed to mid-rail, and that a small increase due to a signal can send the resistance soaring. Also remember that this is a 'typical' condition that may not be correct for an individual part.

For our 'typical' device, a bias point of 0.575V allows us the maximum swing in our 50R switched circuit before we exceed 10% of the 50R as switch resistance (using the better, Fairchild part), but the swing must not exceed 0.575Vpk and should ideally be considerably less in order to avoid voltage nonlinearity of resistance. We may consider a bias of 1V or even more to be acceptable for small signals, but 2.5V is not at all good. If we were to superimpose a 0.575Vpk waveform on the present 2.5V bias level, the resulting +ve peak of 3.075V (for a symmetrical waveform) would  take us close to cutoff, especially for the TI device. The on-resistance would be too high (10R or more) and very device and voltage dependent. All for a (probably mythical) 'typical' device with 5.0V supply and at 25degC.

Half-rail was nice & easy to implement. Equal value resistors do the job, maybe 10k each. In a 50R circuit the resulting 5k in shunt is not going to be a problem.

Possible solution

I would aim at 0.5V bias point, since it feels as if it should be easier; the signal can swing -ve by 0.075V without touching the clamp diode and we can end up with good on-resistance symmetry even for a 1Vpp signal.
Let's assume we only wish to change one of the existing resistors; the 'bottom' one. To get 0.5V from a nominally 4.75V supply with a 10k 'top' resistor, we must drop (4.75-0.5V) in the 10k i.e. 4.25V in 10k. By ratio, to drop 0.5V the 'bottom' resistor must be (10 * 0.5 / 4.25 k) or 1.176k. If we use the next preferred value of 1.2k, will the voltage be OK? It will be (4.75 * 1.2 / (10 + 1.2))V, 0.50892V. This is even closer to our desired 0.575V and sounds acceptable. In our 50R circuit, the parallel load of 1.07k will not be likely to pose a problem; it represents a drop of 5% of the 50R and we already tolerated a rise of 10% due to switch resistance, but we need to be happy with this.

Next we should perform a tolerancing exercise. Maybe we are using 5% resistors, maybe 1%. If they are 5%, the two cases are with (1.14k and 10.5k) and (1.26k and 9.5k) which give 0.465V and 0.556V respectively for our bias, which sounds OK. 1% resistors would give a closer control.

Up to now we have considered a minimum chip supply of 4.75V. We may be able to regulate it much better than this. This is the lowest we should expect. What if it is higher?
The voltage on the FET will rise with the supply. For a 5.25V supply, the FET will see 0.5V more on the gate for 'on' and will conduct more enthusiastically. At the same time, the bias divider will have moved the bias point up by only about a fifth of the supply change; it goes the right way but by less, so we have more margin and things are even better.

How about no change?

If we leave the equal value (half-rail) bias resistors in place, what will be the consequence? It's a very easy 'modifcation'!
Consider our 'typical' device, and let's make it 'typical' for the supply also, +5.0V.
We have a Vgs of half rail, 2.5V, as the bias point of our FET. This, from the graph, corresponds to an 'on' resistance of 7 Ohms (9R for TI parts), not bad but higher than our R target. Our +-0.25V signal will modulate the on-resistance between roughly 6.5 and 7.5 Ohms (for a Fairchild device). This may be totally acceptable... But remember this is for a 'typical' device at 5.0V supply and 25°C chip temperature... And the signal may not be 0.5Vpp.

What about switch Capacitance?

In the past there has been discussion about the 'off' capacitance of these switches. Because there are two sections in parallel used to switch each end of each bandpass filter onto the input and output 'buses', this is probably the most affected area.
Fairchild's latest datasheet (March 2008) from their website specifies this as 2pF per switch, but the older datasheet dated August 1997 (from the Farnell website) gives it as 5pF.
This is a big difference, but I suppose that if they have bothered to change it then we should observe the more recent figure of 2pF.  This gives a feedthrough capacitance of 4pF for the National devices in the bandpass filter, which is perhaps more than we would like. Certainly if it is 5pF (TI is currently specified at 4pF) then two parallel switches at 10pF is rather high.  It is worth noting that Glenn's boards have provision for adding an inductor to null the effect on the highest frequency; this has been used by some builders. But how much do we need to null? Is the switch capacitance 4pF or 10pF? Are they Fairchild or TI parts? What about other stray capacitances (PCB etc)?

What should we do?

  1. First, measure the supply voltage to the device. If it is 5.0V or more then things are not so bad. If it is 4.75V then change the regulator to get more voltage; every little helps a lot, but please remain within the manufacturers' recommended operating conditions, remember their warning and don't push your luck. Recall that the 'typical' figures that we used actually only apply for a 5.00V supply.
  2. Second, see how large the signal might be and consider whether the modulation of resistance is likely to be troublesome. For a few millivolts it will probably not be a problem; for half a volt it probably will. 'Signal' means anything that will appear at the switch; for a radio it could be anything received by the antenna (at the switch on the input of the BPF).
  3. Third, decide whether the value of 'on' resistance is really significant. Will there be untoward signal loss in a 50R path? If so, is it so early in the signal path that amplifying back up to the previous level will increase the noise level excessively? Or is it switching a high-impedance circuit where on-resistance has small effect?
  4. Fourth, trust to good fortune that the devices are all at or below 'typical' threshold voltage. But recall what we found about worst-case devices...
  5. Fifth, if you can and want to play more safely, reduce the bias voltage to as low as you dare. Every little helps.  Don't feel that doing so will give less dynamic range - it will most likely give more. Bias at mid-rail is inviting switch cutoff. Only 1V more positive on signal peaks and the switch will probably open completely, but there is (nominally) 2.5V of range in the negative direction. You will end up with more dynamic range rather than less by reducing the bias!


When using Bus Switches as analogue switches, great care must be taken to avoid setting an operating condition that approaches the cutoff voltage of the single NMOS switching FET.
If we assume that our devices conform to the 'typical' published parameters, which are only valid at 25degC and for a 5.0V supply, then any signal voltage within 1.5V below the +ve supply is in great danger of causing the FET to turn off; it will at least increase the switch resistance depending on the voltage. 

Do not treat these devices as having rail-to-rail signal switching capability; they are not CMOS switches and do not have the benefits that CMOS switches offer. As with CMOS switches, the on-resistance is not linear with applied switch voltage, but unlike CMOS switches they actually turn 'off' as the signal exceeds a certain level.  Due to the gate threshold of the N-Channel switch, mid-rail is not a good bias point if lowest on-resistance and maximum signal range are desired.

For switching in a 50R environment, the FET on-resistance should be a small part of the 50R, or unwanted attenuation and even voltage non-linearity will occur. This is worse with TI devices, SN74CBT3126, than with Fairchild FST3126 parts, which are better in all respects and should always be the choice. Some TI bus switches are intended for 3.3V supplies, but these contain gate voltage-boosters and must never be used for RF switching.
In addition, to maintain a switch on-resistance which is less than 5R (10% of the 50R path), the switched voltage must never exceed +1.5V even with Fairchild devices, even if our supply is 5.0V.  If we use TI devices, the voltage must not exceed +0.5V under the same conditions; not very useful!

It may be that an on-resistance greater than 5R is deemed accetable, but remember that it becomes increasingly affected by small variations of amplitude (i.e. is non-linear) and may accentuate non-linear distortion products of the signals being passed (intermodulation distortion).

The normally-used 'mid-rail' biassing and a.c. coupling of signals does not meet the above criteria, even statically. The static on-resistance is 7.5R for Fairchild, 9R for TI, rising rapidly as the signal becomes more positive. This can be overcome, giving a reasonable dynamic range, by reducing the bias voltage.
To maximise the linear dynamic range when using Bus Switches as analogue switches, the bias point for an a.c. coupled circuit should be no greater than 0.575V if we wish to maintain an on-resistance of <5R for maximum signal-voltage range with Fairchild parts, or 0.25V with TI devices. The voltage can then swing between 0V and (2 x bias) without the on-resistance exceeding 5R  and without dramatic non-linearity of on-resistance. With TI devices this limits the switched a.c. signal to 0.25Vpk, making the Fairchild device a far better choice at 0.575Vpk.
Even with a larger signal, it is possible to swing maybe 0.3V below the 0V supply before the protection diode begins to conduct. The positive increase of 0.3V to 0.875V (for a symmetrical signal) will give an increased on-resistance, but this is still far better than if a mid-rail bias were used, when even a typical Fairchild part has a rapidly rising on-resistance of 11R and a TI part is unuseable.

Real Examples

After writing this, I encountered two very real examples of this: bus switch elements actually running close enough to the cutoff point to clip the positive peaks (by turning 'off' as the signal reaches the Vgs threshold).
One of these is also shown in the 2nd IF Tx page; it seriously clips the high-impedance signal from the CODEC DAC:
Bus switch clips the DAC +ve peaks
Shunting R631 with 5k6 cures it, as predicted.

This is what it looks like on Glenn's latest STAR using TI bus switches:
Clipping CODEC DAC with a TI bus switch
Once again, the 5k6 shunt over R631 cures it.

The other example is in the MR, in a 50R path. The transmit IF signal into the diplexer is switched in IC505, but the amplitude is high enough (untrimmed) that the positive peak is clipped (view at IC505 pin 12 where it feeds the diplexer):
MR clipping in IC512
I have left the full 'scope face visible. The 'Y' origin is at the lowest graticule line. Y scale is 0.5V/div, so clipping occurs at +3.25V, no surprises. Of course, at levels near this there will be compression as the FET on-resistance rises; some of this is actually visible.  The usual cure applies, shunt R520, this time with 1k2 since R520 is 2k2 rather than 10k.

My STAR uses Fairchild bus switches, which have better characteristics (lower Vgs and Ron) than TI.

What will M0RJD do?

Good question! Since the old fool has taken the time and trouble to look at these things, it would be nice to know his intentions!
I will shunt all the 'bottom' resistors in the bias networks throughout in order to improve the dynamic range available and to prevent substantial non-linearity. A  drop in bias from half-rail to say a third of the rail would give better conditions regardless of level and impedance. At 1.4V bias the signal can swing 1.4V negative before it has any danger whatsoever of clipping, and 1.35V of positive swing before the on-resistance exceeds 8R, which might still be deemed acceptable. Beyond that, the on-resistance increases too rapidly to be useful. Using a 10k 'top' resistor, I need a 3.9k bottom resistor. Maybe shunting the bottom 10k with 5k6 would be simplest, giving 3.6k.
In the RF sections, a 2k2+2k2 network is used rather than 10k+10k. For most of these, a 1k2 shunt on the lower resistor is appropriate. Beware R510, used for biassing the H-mode mixer switches. Because of the higher (6V2) supply a larger shunt value is appropriate, around 3.9k will be appropriate to place the bias centrally within the switch range.

Most of the switching in STAR is at very low level, so it is possible that no improvement will be noticeable; it depends. But it cannot possibly make it worse.

I have fortuitously already built my own STAR with National Semiconductor LP2950C5V0 regulators in place of the more normal (and specified) 78L05 devices, since I had loads of them and have found them to be life-savers many times in the past.
National's LP2950C5V0 has a tested limit at 25deg C of 4.975V to 5.025V, which is 5.0V±25mV.
78L05 is variously specified as ±5% or ±0.2V, at best 5.0V±200mV, depending on manufacturer (there are many).
I will expect that, in the absence of any fault, my supplies will be OK at least, if they come from an LP2950C5V0.

Why should we believe it?

I have been asked by [anonymous] why he should change all his switch bias points when the original design works so well as it is. He asks how he can be sure that changing it will not break something - (setup | IP3 | sensitivity | MDS | calibration | whatever)? 
It is, of course, wise to be cautious. You, as an individual, must decide for yourself. Sorry, but I can only present the information as I have done, and leave you to draw whatever conclusion you wish.
If you think that what I have said is balderdash, that is entirely your priviledge. Please let me know if this is what you decide, and why you believe it to be so.

I have presented information and calculations based on manufacturers' published data, and I believe that my calculations and conclusions are sound. If I were designing equipment using Bus Switches as analogue switches, I would go through exactly the same steps and, unless I have made an error, end up with exactly the same figures and conclusions. The main thing that I would question is whether Bus Switches would be the right device to use, but that is an entirely different scenario. They work in practice, but 'could do better if they tried harder', as one of my School reports said many years ago.

I am very aware that every design I have seen using bus-switches in this way, not just STAR,  sets the bias at mid-rail. This doesn't make it right.

If you prefer disbelief or scepticism on the basis that someone, sometime in the past, used different values, without seeing or asking to see their calculations, then so be it. It really doesn't bother me. 
You can check and double-check every step of my reasoning and calculations - can you do that with the original design, or is it just based on trust? If the latter, I suggest that you also look at some of my other pages, then come here again.
Feel free to show me the original calculations upon which the bias level was based - I have not seen these so cannot comment on them.

Will your unit break if you change the bias?  Why should it - you are improving the linearity and dynamic range; if this breaks it would you not be surprised? As long as you take care not to upset the working point of any other devices then nothing else will notice (I believe that the Bus Switches are all a.c. coupled except for my own modification, where the d.c. coupling actually benefits several switches all at once). You can always revert to the original design if you wish, it is easy enough, as with all the modifications I have suggested on these pages.  Of course, when modifying things, you may accidentally break something. I can't guarantee that your hand will be steady and your soldering perfect. Mine certainly isn't!

Will the calibration change? Well, you may see more signal as a result of reducing the on-resistance of switches in the 50R signal paths, so yes, it might require re-calibration. Would you rather have a better signal path or not? You decide.

Will the sensitivity improve? It might, if the bus switches in the Band Pass Filter (BPF) are losing your valuable signal before it gets into those noisy amplifiers.
Will it get worse? Tell me why you think it would. Seriously; I would like to know.

What about distortion and intermodulation?  OK, perhaps you can explain why having a smaller dynamic range with the original half-rail bias (before the switch becomes non-linear) will give better distortion and intermodulation performance? You may not notice any difference after changing the bias as I suggest, but why would better dynamic range and reduced non-linearity make it worse? Let me know why, please.

I really can't be bothered to try to measure the 'before' and 'after' performance for you, since I have no doubt that sound design is, in itself, worth while. I'm not trying to sell you anything; please don't suggest I should prove that there is a tangible improvement. However, if you perform any measurements, and send me the results, I will happily add them here and credit you with them if you permit.

Step-by-Step guide to modifying PICASTAR

This is a tabular list of pulldown resistors on PICASTAR ComboBOARD bus switches, showing both new values and recommended shunt resistors to use over existing components.
The chosen values maximise dynamic range whilst avoiding the cutoff region of the FETs.
I have allowed for the signal to swing slightly below 0V which is OK until it hits clamp diodes.
For 1.35V bias on 5V supply, symmetrical swing is +-1.6V, 3.2Vpp.  Above 2.8V the FET on-resistance is becoming too high in 50R path, especially with TI devices (10R and rising rapidly).
NOTE: Sheets 1, 2, 3, 4, 5, 6, 7, 9, 13 and 16 do not include bus switches.
1k2 (Thanks, G4CIZ)
1k8 (see note below)

BPF 10 R1104
BPF 10 R1202
BPF 10 R1204
BPF 10 R1302
BPF 10 R1304




Note: for R510 on IC504, Vcc is 6v2, so bias is 2v0 for reasonable symmetry of on-resistance. Maximum signal before clipping is now 4.6Vpp approximately, was originally approximately 3Vpp before +ve peak clipping.
Thanks also to Tony G4CIZ for noticing that I had originally omitted R517.

This is also available as a spreadsheet in XLS format.


May I remind you that any change from the published PICASTAR design will make your unit non-standard. You may not receive support from the STAR team if something goes wrong. I am unable to offer any support or guarantee whatsoever; I'm too old for that sort of thing <g>. I have presented all the design information accurately, to the best of my knowledge and limited ability. If you find an error please let me know.
Maybe you feel that the changes I have described should become an 'official modification'. New builders could then incorporate the changes from day one. If this is your opinion, then why not say so on the Picastar-users group mailing list on yahoogroups.com?

© 2010 M0RJD