AD9951 Output Level

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The Pic-A-STAR DDS produces a digitally synthesised frequency to be the First Local Oscillator for the STAR. It employs a stable reference oscillator to clock the AD9951 internal logic, which outputs a complementary current-sinking a.c. signal at the two outputs. Unlike the previous AD9850 and AD9851 DDS devices, the AD9951 uses 1.8V logic internally to achieve a much higher maximum clockrate and to provide a 14-bit output DAC in place of 10-bits.

The output level of the AD9951 device when used in the STAR configuration can be assessed in two ways. One uses a simple calculation to determine the peak voltage outputs; the other, taken from Analog Devices Application Note AN912, first calculates output power using equations derived in the Application Note.

STAR DDS output arrangement

STAR DDS output circuit

Simple Method

The datasheet for AD9951 specifies the current on each output as varying from Iset to 0mA, each in antiphase with the other output. This represents Iset peak-to-peak per output. The datasheet also says:

"Two complementary outputs provide a combined full-scale output current (IOUT). Differential outputs reduce the amount of common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio. The full-scale current is controlled by an external resistor (RSET)..."

The STAR uses a value of RSET (3k9) that produces a combined output current of 10mA.

When one output is giving 10mA (in our case) the other provides 0mA into the load; the *combined* current is 10mA. This means that the mid-point of the sine output ('zero crossing') is at 5mA, when each output delivers the same proportion of the set current, half of the 10mA.

At a.c., when the voltage at one end of the primary moves by an amount, it reflects at the other end of the primary as an equal amount but of opposite polarity. This means that each of the 100R resistors has the same applied voltage, but of opposite polarity. Since resistors are not polarity conscious, the net effect is as of a single load of 50R seen by each output, in parallel with the transformed load on the secondary.

Considering the condition where output-1 is sinking the whole 10mA and output-2 is sinking no current (i.e. one peak, call it 'peak-1'). The load it sees is its own 100R to AVdd, plus the opposite 100R, which it is driving through the transformer action but with the opposite polarity.
The two resistors therefore share the 10mA, or looking at it another way are functionally in parallel.
The voltage on each resistor is 10mA x 50R (2 resistors 'in parallel') or half the current in each resistor, 5mA x 100R, however you wish to see it. The voltage on peak-1 is +500mV on the 'idle' 0mA pin (output-2) and -500mV on the 'active' 10mA pin (output-1).

On the opposite peak, 'peak-2', the situation reverses, output-1 is sinking no current and output-2 the whole 10mA, again driving both resistors in the same way as before. The same thing happens as above, except that the relative polarities reverse. By the same argument, the voltage on the 'idle' pin, output-1, is now -500mV and on output-2 is +500mV. This is clearly a primary voltage of 1Vpp.
This considers the peaks, for the rest of the cycle the currents (and voltages) are lower.

So, from the above, the signal stays just within the +-500mV compliance range with no load.
When loaded with the 200R filter, the voltages all halve since the pin load impedance halves.

The loaded (normal) condition produces a full primary voltage of +-500mV, or 1Vpp. This is perfectly safe for the DDS, which has a voltage swing of +-250mV on each output pin. The specified maximum compliance voltage, which must not be exceeded, is +-500mV relative to AVdd, which is the connection of the transformer centre tap.

In the standard 200R STAR reconstruction filter, the input impedance actually rises to over 300R at some frequencies. If the DDS did not have the two 100R resistors connected to the outputs, and the transformer had been designed to make best use of the compliance range of the AD9951 (as was done with the AD9850/51 transformer-coupled circuit), then when the filter input impedance rises above 200R the chip would see voltages in excess of the compliance range, which would probably destroy it. The same thing would happen if the filter load were disconnected.

The present design for AD9951 keeps the device safe from accidental damage by limiting the output pin swings to be within the compliance range. The price to pay is that, being source-terminated, the output voltage is only 1Vpp.

The description above has ignored the effect of rapid current changes into the transformer windings. For a high output frequency relative to the reference clock, the output sysnthesis will consist of few samples per cycle, in the limit only two at the Nyquist frequency. At these steps, the device tries to make step changes in the output current, which, together with the leakage inductance of the primary, can give voltage spikes that may exceed the compliance voltage range. The resistors damp such spikes considerably; they are further reduced by the bifilar primary winding, which decreases leakage inductance.
In normal, loaded operation this efect is not a problem, but unloaded operation may momentarily exceed the compliance range.

It would be normal to run the DDS input (sample) clock at the highest convenient frequency, in order to minmise output signal reduction due to sin(x)/x rolloff. This also serves to reduce the steps on the output pins as the waveform commutates, again reducing any damaging inductive spike energy.

AN-912 Method

Only a part of the App Note AN-912 is needed to resolve the conditions in our circuit.
AN-912 can be downloaded from the Analog Devices Website.

Referring to the equations on Page 5, which apply to us:

From Fig 6, "DAC with reconstruction filter":
The transformer ratio 1:N is for the full primary, not a half, so our 'N' is 1 (the winding is 3+3:6). Our nominal RL is the filter Z, approximately 200R.

From equation (9):
R0 = RL/(2N2) gives R0 = 200 / (2 * 12) = 200/2 = 100R [a]
This is the required value for each output-pin load resistor and is what we have in the design. It is actually pretty intuitive, since the DDS outputs are current sources and do not contribute to the load impedance.

Now, because we have the condition of impedance matching (where Zs=ZL), we can use equation (16) to find the power in the load, PL:
PL=(RL/2)(Imax/4N)2 (equation 16)
Our Imax is set at 10mA by the 3K9 on DDS pin 24 (DAC_Rset)
RL = 200R as above; N=1 as above.
So PL = (200/2) * (0.01A / 4)2
PL = 100 * (0.0025)2
PL = 0.625mW

We are perhaps more interested in the voltage out of the transformer than the power into the load (I am, anyway),
So Use the normal PL=V2/R to work out the r.m.s. value:
0.625mW = V2 / 200R
V2 = 0.625mW * 200R
VL = 0.3536Vrms

Now it's easy to convert to peak-peak for a sinewave, Vpp = Vrms * 2 * sqr(2)

V = 1Vpp [b]

This value for V is the voltage p-p across the (full primary) or secondary of the transformer, since it is 1:1 overall.
It is the loaded voltage, and for a perfectly coupled transformer is also the voltage input to the reconstruction filter.
The actual amplitude out of the reconstruction filter may be less than this due to sin(x)/x rolloff, assuming a perfect filter with perfect termination (neither is perfect).

Now let's see what this is at the pins of the DDS:
The voltage input to the 200R filter is 1Vpp from [b]
The voltage on each DDS output pin is half this, because the primary is centre-tapped, so is 0.5Vpp [c]
Because the transformer acts to dispose this equally each side of the centre-tap, which is at AVdd, then
The voltage on each output wrt AVdd is 0.25Vpk [d]

Which is, amazingly, what the simple view of it produced!

Now I really should repeat the above for RL = infinity, to see what the output and pin voltages are with no load, but since no power is delivered to an infinite load the equations above don't work.
However, in a matched impedance circuit, we know what the source voltage does when there is no load (it doubles), so the

Maximum unloaded voltage per DDS pin is 2 * 0.25Vpk = 0.5Vpk [e].

This is within the compliance rating (just) as before, ignoring inductive spikes from output commutation current steps into the transformer primary leakage inductance.

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